Wafer level integration package

1. A semiconductor package, comprising:

a double-sided substrate having an active surface and second surface opposite the active surface;

a through-hole interconnect structure extending through the double-sided substrate from the active surface to the second surface;

a first conductive layer formed over the active surface and electrically connected to the through-hole interconnect structure;

a semiconductor die mounted to the active surface of the double-sided substrate and electrically connected to the first conductive layer;

an encapsulant deposited over the semiconductor die and double-sided substrate and further along a sidewall of the double-sided substrate extending from the active surface to the second surface;

a second conductive layer formed over the second surface and electrically connected to the through-hole interconnect structure; and

a dielectric layer formed over the second surface creating a land while surrounding and isolating the second conductive layer.

2. The semiconductor package of claim 1 , wherein the semiconductor die includes a flip chip semiconductor device, wire bond semiconductor device, or passive component.

3. The semiconductor package of claim 1 , further including a heat spreader structure disposed over the semiconductor die.

4. The semiconductor package of claim 1 , further including an electromagnetic interference shield disposed over the die.

5. The semiconductor package of claim 1 , further including a passive component mounted to the double-sided substrate and electrically connected to the first conductive layer.

6. The semiconductor package of claim 1 , further including a plurality of die stacked in a package-in-package arrangement.

7. The semiconductor package of claim 1 , wherein a surface of the semiconductor die is exposed from the encapsulant.

8. The semiconductor package of claim 1 , further including an underfill material disposed between the semiconductor die and the double-sided substrate to provide structural support.

9. A semiconductor package, comprising:

a double-sided substrate having an active surface and second surface opposite the active surface;

a conductive via formed from the active surface and extending through the double-sided substrate to the second surface;

a first conductive layer formed over the active surface and electrically connected to the conductive via;

a semiconductor component mounted to the active surface of the double-sided substrate and electrically connected to the first conductive layer and conductive via;

an encapsulant deposited over the semiconductor component, over the double-sided substrate, and in a channel formed along a side of the double-sided substrate;

a second conductive layer formed over the second surface and electrically connected to the conductive via; and

a dielectric layer formed over the second surface surrounding and isolating the second conductive layer.

10. The semiconductor package of claim 9 , wherein the semiconductor component includes a flip chip semiconductor device, wire bond semiconductor device, or passive component.

11. The semiconductor package of claim 9 , further including a heat spreader structure disposed over the semiconductor component.

12. The semiconductor package of claim 9 , further including an electromagnetic interference shield disposed over the semiconductor component.

13. The semiconductor package of claim 9 , further including a passive component mounted over the double-sided substrate and electrically connected to the first conductive layer.

14. The semiconductor package of claim 9 , further including a plurality of semiconductor components stacked in a package-in-package arrangement.

15. The semiconductor package of claim 9 , wherein a surface of the semiconductor component is exposed from the encapsulant.

16. A semiconductor package, comprising:

a substrate with a wafer-form factor having an active surface and second surface opposite the active surface;

a conductive via formed between the active surface and second surface;

a first conductive layer formed over the active surface and electrically connected to the conductive via;

a semiconductor component mounted over the substrate and electrically connected to the first conductive layer and the conductive via;

a channel extending from the active surface partially through the substrate;

an encapsulant deposited over the substrate, semiconductor component, and into the channel wherein:

the substrate is backgrinded to expose the encapsulant in the channel and the conductive via; and

an interconnect structure formed over the second surface.

17. The semiconductor package of claim 16 , wherein the interconnect structure includes:

a contact pad formed over the second surface and electrically connected to the conductive via; and

a dielectric layer formed over the second surface and around the contact pad.

18. The semiconductor package of claim 16 , further including a heat spreader structure disposed over the semiconductor component.

19. The semiconductor package of claim 16 , further including an electromagnetic interference shield disposed over the semiconductor component.

20. The semiconductor package of claim 16 , further including an underfill material disposed between the semiconductor component and substrate to provide structural support.

21. A semiconductor package, comprising:

a substrate;

a first conductive layer formed over a first surface of the substrate;

a conductive via formed between the first conductive layer and a second surface of the substrate;

a semiconductor component mounted to the substrate and electrically connected to the first conductive layer; and

an encapsulant deposited over the semiconductor component and covering a side of the substrate from the first surface to the second surface of the substrate.

22. The semiconductor package of claim 21 , further including an interconnect structure formed over the bottom surface of the substrate.

23. The semiconductor package of claim 21 , further including a heat spreader structure disposed over the semiconductor component.

24. The semiconductor package of claim 21 , further including an electromagnetic interference shield disposed over the semiconductor component.

25. The semiconductor package of claim 21 , further including a plurality of semiconductor components stacked in a package-in-package arrangement.