Patent Assignment
Reel/Frame 065236/0767
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0309. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Recorded: 2023-09-11
Received: 2023-10-16
Pages: 12
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(75)
Wirelessly Configuring Climate Control System Controls
App. No. 18/380,493
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STACKED DIE SEMICONDUCTOR DEVICE HAVING CIRCUIT TAPE
App. No. 12/631,476
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED PASSIVE CIRCUIT ELEMENTS INTERCONNECTED TO THROUGH HOLE VIAS
App. No. 12/627,884
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
App. No. 12/623,351
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE SUBSTRATE HAVING CORNER CONTACTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/612,630
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WAFER LEVEL INTEGRATION PACKAGE
App. No. 12/493,108
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ETCHED RING AND DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/473,239
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/412,064
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LAYERED PACKAGING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/408,662
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LEADED STACKED PACKAGES HAVING ELEVATED DIE PADDLE
App. No. 12/353,020
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/340,638
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INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIAS WITH PARTIAL DEPTH METAL FILL REGIONS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/334,347
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INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIA WITH DIRECT INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/333,297
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR DIE AFTER FORMING A BUILD-UP INTERCONNECT STRUCTURE
App. No. 12/332,277
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
App. No. 12/331,682
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SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
App. No. 12/329,778
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A PROTRUSION ON AN INNER STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/329,482
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERPOSER PACKAGE WITH THROUGH SILICON VIAS
App. No. 12/325,587
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ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR
App. No. 12/276,297
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EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 12/266,313
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
App. No. 12/238,183
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QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/236,437
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH-FREQUENCY CIRCUIT STRUCTURE AND METHOD THEREOF
App. No. 12/212,524
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER
App. No. 12/207,459
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SEMICONDUCTOR DEVICE AND METHOD OF LASER-MARKING WAFERS WITH TAPE APPLIED TO ITS ACTIVE SURFACE
App. No. 12/205,695
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DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/203,332
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SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING A THERMAL DISSIPATION PATH THROUGH RDL AND CONDUCTIVE VIA
App. No. 12/173,504
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SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED PASSIVE DEVICES
App. No. 12/167,146
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INTEGRATED CIRCUIT PACKAGE SYSTEM STACKABLE DEVICES
App. No. 12/146,101
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METHOD AND APPARATUS FOR WAFER LEVEL INTEGRATION USING TAPERED VIAS
App. No. 12/137,242
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SEMICONDUCTOR DEVICE AND METHOD OF CONNECTING A SHIELDING LAYER TO GROUND THROUGH CONDUCTIVE VIAS
App. No. 12/136,723
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SEMICONDUCTOR DEVICE HAVING ELECTRICAL DEVICES MOUNTED TO IPD STRUCTURE AND METHOD OF SHIELDING ELECTROMAGNETIC INTERFERENCE
App. No. 12/133,133
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADED PACKAGE
App. No. 12/132,121
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PACKAGE SYSTEM INCORPORATING A FLIP-CHIP ASSEMBLY
App. No. 12/122,631
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH AN ENCAPSULANT CAVITY AND METHOD OF FABRICATION THEREOF
App. No. 12/057,299
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FLIP CHIP INTERCONNECTION STRUCTURE WITH BUMP ON PARTIAL PAD AND METHOD THEREOF
App. No. 12/055,152
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MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXPOSED EXTERNAL INTERCONNECTS
App. No. 12/054,682
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MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE
App. No. 12/054,701
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING MODULE
App. No. 12/053,760
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING OXIDE LAYER ON SIGNAL TRACES FOR ELECTRICAL ISOLATION IN FINE PITCH BONDING
App. No. 12/051,349
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTERNAL INTERCONNECTS WITHIN A DIE PLATFORM
App. No. 12/036,056
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MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING INTERPOSER
App. No. 11/965,641
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SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE
App. No. 11/965,160
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SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
App. No. 11/964,529
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE MODULE
App. No. 11/958,603
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE FOR ENCAPSULATED DIE HAVING PRE-APPLIED PROTECTIVE LAYER
App. No. 11/957,101
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING AND ANTI-FLASH STRUCTURE
App. No. 11/954,613
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SEMICONDUCTOR WAFER LEVEL INTERCONNECT PACKAGE UTILIZING CONDUCTIVE RING AND PAD FOR SEPARATE VOLTAGE SUPPLIES AND METHOD OF MAKING THE SAME
App. No. 11/951,729
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
App. No. 11/947,377
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METHOD OF FORMING AN INDUCTOR ON A SEMICONDUCTOR WAFER
App. No. 11/936,461
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SEMICONDUCTOR WAFER HAVING THROUGH-HOLE VIAS ON SAW STREETS WITH BACKSIDE REDISTRIBUTION LAYER
App. No. 11/861,244
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICE UNITS
App. No. 11/858,588
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/858,861
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH SIDE-BY-SIDE AND OFFSET STACKING
App. No. 11/849,087
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STACKABLE PACKAGE BY USING INTERNAL STACKING MODULES
App. No. 11/771,086
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CIRCUIT SYSTEM WITH CIRCUIT ELEMENT
App. No. 11/770,690
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANGING CONNECTION STACK
App. No. 11/769,512
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH TOP AND BOTTOM TERMINALS
App. No. 11/768,730
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING
App. No. 11/766,787
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ULTRA THIN BUMPED WAFER WITH UNDER-FILM
App. No. 11/745,045
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE
App. No. 11/670,862
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STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/608,827
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING THIN PROFILE TECHNIQUES
App. No. 11/608,123
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INTEGRATED CIRCUIT STACKING SYSTEM WITH INTEGRATED PASSIVE COMPONENTS
App. No. 11/538,806
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INTEGRATED CIRCUIT SYSTEM WITH WAFER TRIMMING
App. No. 11/532,455
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWN-SET DIE PAD AND METHOD OF MANUFACTURE THEREOF
App. No. 11/462,247
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INTEGRATED CIRCUIT HEAT SPREADER STACKING METHOD
App. No. 11/456,846
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STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE
App. No. 11/381,683
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EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/379,332
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INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG
App. No. 11/279,131
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NET SPACER
App. No. 11/278,411
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HYBRID STACKING PACKAGE SYSTEM
App. No. 11/278,420
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SYSTEM FOR REMOVAL OF AN INTEGRATED CIRCUIT FROM A MOUNT MATERIAL
App. No. 11/276,945
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INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/276,727
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MULTI-CHIP PACKAGE SYSTEM
App. No. 11/326,211
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