IP Library Granted Patent US 7,785,929
Granted Patent B2
US 7,785,929 · App. 12/054,682 · Granted Aug 31, 2010

Mountable integrated circuit package system with exposed external interconnects

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,785,929
App. No.
12/054,682
Granted
Aug 31, 2010
Kind
B2
Abstract

The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation.

Claims (56)

1. A method for manufacturing a mountable integrated circuit package system comprising:

providing an inner integrated circuit package including a first external interconnect having a shoulder;

connecting an intraconnect between a second external interconnect and the shoulder; and

forming an outer encapsulation over the inner integrated circuit package and fully enclosing the intraconnect, the outer encapsulation partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation.

2. The method as claimed in claim 1 further comprising:

mounting a first stacking integrated circuit device over the inner integrated circuit package; and

connecting a first inner interconnect between the first stacking integrated circuit device and the first external interconnect.

3. The method as claimed in claim 1 wherein providing the inner integrated circuit package includes:

forming an inner encapsulation over an inner integrated circuit device connected to the first external interconnect, the inner encapsulation exposing the shoulder and an outer tip of the first external interconnect, and partially exposing an inner tip of the first external interconnect.

4. The method as claimed in claim 1 further comprising mounting a second stacking integrated circuit device over the first external interconnect and the outer encapsulation.

5. The method as claimed in claim 1 wherein providing the inner integrated circuit package includes forming an inner encapsulation covering an inner integrated circuit device mounted over a die-attach paddle and the die-attach paddle exposed from the outer encapsulation.

6. A method for manufacturing a mountable integrated circuit package system comprising:

providing an inner integrated circuit package having an inner integrated circuit device mounted to a die-attach paddle and connected to a first external interconnect having an inner tip, a shoulder, and an outer tip;

connecting an intraconnect between a second external interconnect and the shoulder; and

forming an outer encapsulation over the inner integrated circuit package and fully enclosing the intraconnect, the outer encapsulation partially exposing the outer tip on a top encapsulation side and the second external interconnect on a bottom encapsulation side.

7. The method as claimed in claim 6 further comprising:

mounting a first stacking integrated circuit device over a second paddle side of the die-attach paddle; and

connecting a first inner interconnect between the first stacking integrated circuit device and a second inner tip side of the inner tip.

8. The method as claimed in claim 6 wherein providing the inner integrated circuit package includes:

mounting the inner integrated circuit device over a first paddle side of the die-attach paddle;

connecting a second inner interconnect between the inner integrated circuit device and a first inner tip side of the inner tip; and

forming an inner encapsulation over the inner integrated circuit device, the first paddle side, the second inner interconnect, the first inner tip side, and partially exposing a second inner tip side of the inner tip.

9. The method as claimed in claim 6 further comprising:

mounting a first stacking integrated circuit device over the inner integrated circuit package; and

connecting a first inner interconnect between the first stacking integrated circuit device and the shoulder.

10. The method as claimed in claim 6 wherein forming the outer encapsulation includes:

forming the outer encapsulation over the inner integrated circuit package;

partially exposing the outer tip at the top encapsulation side, the second external interconnect on the bottom encapsulation side; and

exposing a second paddle side of the die-attach paddle on the bottom encapsulation side.

11. A mountable integrated circuit package system comprising:

an inner integrated circuit package including a first external interconnect having a shoulder;

an intraconnect connected between a second external interconnect and the shoulder; and

an outer encapsulation formed over the inner integrated circuit package and fully enclosing the intraconnect, the outer encapsulation partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation.

12. The system as claimed in claim 11 further comprising:

a first stacking integrated circuit device mounted over the inner integrated circuit package; and

a first inner interconnect connected between the first stacking integrated circuit device and the first external interconnect.

13. The system as claimed in claim 11 wherein the inner integrated circuit package includes:

an inner integrated circuit device connected to the first external interconnect; and

an inner encapsulation formed over the inner integrated circuit device, and exposing the shoulder and an outer tip of the first external interconnect, and partially exposing an inner tip of the first external interconnect.

14. The system as claimed in claim 11 further comprising a second stacking integrated circuit device mounted over the first external interconnect and the outer encapsulation.

15. The system as claimed in claim 11 wherein providing the inner integrated circuit package includes:

a die-attach paddle exposed from the outer encapsulation;

an inner integrated circuit device over the die-attach paddle; and

an inner encapsulation covering the inner integrated circuit device.

16. The system as claimed in claim 11 wherein the inner integrated circuit package includes the inner integrated circuit device mounted to a die-attach paddle and connected to the first external interconnect having an inner tip, the shoulder and an outer tip.

17. The system as claimed in claim 16 further comprising:

a first stacking integrated circuit device mounted to a second paddle side of the die-attach paddle; and

a first inner interconnect connected between the first stacking integrated circuit device and a second inner tip side of the inner tip.

18. The system as claimed in claim 16 wherein the inner integrated circuit package includes:

the inner integrated circuit device mounted to a first paddle side of the die-attach paddle;

a second inner interconnect connected between the inner integrated circuit device and a first inner tip side of the inner tip; and

an inner encapsulation formed over the inner integrated circuit device, the first paddle side, the second inner interconnect, the first inner tip side, and partially exposing a second inner tip side of the inner tip.

19. The system as claimed in claim 16 further comprising:

a first stacking integrated circuit device mounted over the inner integrated circuit package; and

a first inner interconnect connected between the first stacking integrated circuit device and the shoulder.

20. The system as claimed in claim 16 wherein the outer encapsulation includes the outer encapsulation formed over the inner integrated circuit package, partially exposing the outer tip at the top encapsulation side, the second external interconnect on the bottom encapsulation side, and exposing a second paddle side of the die-attach paddle on the bottom encapsulation side.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0309. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 11, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0767 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0309 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2008
From: CAMACHO, ZIGMUND RAMIREZ; ADVINCULA, ABELARDO JR. HADAP; BATHAN, HENRY DESCALZO; TAY, LIONEL CHIEN HUI
To: STATS CHIPPAC LTD.
Reel/Frame 020724/0066 →