IP Library › Assignment 052924/0007
Patent Assignment
Reel/Frame 052924/0007

RELEASE OF SECURITY INTEREST

Recorded: 2020-06-12 Received: 2020-06-12 Pages: 27
Assignor
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications (100)
METHOD FOR MAKING A STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE
App. No. 12/784,434
→
METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE WITH FINE PITCH LEAD FINGERS
App. No. 12/767,670
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 12/730,171
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK AND METHOD OF MANUFACTURE THEREOF
App. No. 12/690,092
→
STACKED DIE SEMICONDUCTOR DEVICE HAVING CIRCUIT TAPE
App. No. 12/631,476
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED PASSIVE CIRCUIT ELEMENTS INTERCONNECTED TO THROUGH HOLE VIAS
App. No. 12/627,884
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
App. No. 12/623,351
→
STACKABLE MULTI-CHIP PACKAGE SYSTEM WITH SUPPORT STRUCTURE
App. No. 12/615,195
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE SUBSTRATE HAVING CORNER CONTACTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/612,630
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
App. No. 12/572,568
→
STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
App. No. 12/571,234
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THROUGH SEMICONDUCTOR VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/562,702
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CIRCUITRY STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/562,722
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/557,481
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A TIERED SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/538,098
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECTION SUPPORT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/484,131
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ETCHED RING AND DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/473,239
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 12/472,236
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INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/413,302
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/412,064
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LAYERED PACKAGING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/408,662
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
App. No. 12/391,807
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CARRIER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/360,644
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LEADED STACKED PACKAGES HAVING ELEVATED DIE PADDLE
App. No. 12/353,020
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/340,638
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INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIA WITH DIRECT INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/333,297
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
App. No. 12/331,682
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED TERMINAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/331,416
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SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
App. No. 12/329,778
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A PROTRUSION ON AN INNER STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/329,482
→
ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR
App. No. 12/276,297
→
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 12/266,313
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
App. No. 12/238,183
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT
App. No. 12/238,153
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING
App. No. 12/237,291
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QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/236,437
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SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD
App. No. 12/235,144
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METHOD OF FORMING A WAFER LEVEL PACKAGE WITH RDL [[BUMP]] INTERCONNECTION OVER ENCAPSULANT BETWEEN BUMP AND SEMICONDUCTOR DIE
App. No. 12/235,000
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH-FREQUENCY CIRCUIT STRUCTURE AND METHOD THEREOF
App. No. 12/212,524
→
METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 12/207,986
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER
App. No. 12/207,459
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BALL GRID ARRAY PACKAGE STACKING SYSTEM
App. No. 12/206,383
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SEMICONDUCTOR DEVICE AND METHOD OF LASER-MARKING WAFERS WITH TAPE APPLIED TO ITS ACTIVE SURFACE
App. No. 12/205,695
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DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/203,332
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION
App. No. 12/201,896
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING A THERMAL DISSIPATION PATH THROUGH RDL AND CONDUCTIVE VIA
App. No. 12/173,504
→
PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION
App. No. 12/171,890
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INTEGRATED CIRCUIT PACKAGE SYSTEM STACKABLE DEVICES
App. No. 12/146,101
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STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION
App. No. 12/146,411
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SEMICONDUCTOR DEVICE AND METHOD OF CONNECTING A SHIELDING LAYER TO GROUND THROUGH CONDUCTIVE VIAS
App. No. 12/136,723
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SEMICONDUCTOR DEVICE HAVING ELECTRICAL DEVICES MOUNTED TO IPD STRUCTURE AND METHOD OF SHIELDING ELECTROMAGNETIC INTERFERENCE
App. No. 12/133,133
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADED PACKAGE
App. No. 12/132,121
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD
App. No. 12/128,116
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PACKAGE SYSTEM INCORPORATING A FLIP-CHIP ASSEMBLY
App. No. 12/122,631
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH AN ENCAPSULANT CAVITY AND METHOD OF FABRICATION THEREOF
App. No. 12/057,299
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RIGID LOCKING LEAD
App. No. 12/055,642
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MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXPOSED EXTERNAL INTERCONNECTS
App. No. 12/054,682
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MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE
App. No. 12/054,701
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING MODULE
App. No. 12/053,760
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
App. No. 12/052,910
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING OXIDE LAYER ON SIGNAL TRACES FOR ELECTRICAL ISOLATION IN FINE PITCH BONDING
App. No. 12/051,349
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PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS
App. No. 12/051,625
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PACKAGE-ON-PACKAGE SYSTEM WITH INTERNAL STACKING MODULE INTERPOSER
App. No. 12/051,280
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BALL GRID ARRAY PACKAGE SYSTEM
App. No. 12/050,400
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INTEGRATED CIRCUIT WITH STEP MOLDED INNER STACKING MODULE PACKAGE IN PACKAGE SYSTEM
App. No. 12/045,646
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SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR DIE EACH HAVING IPD AND METHOD OF REDUCING MUTUAL INDUCTIVE COUPLING BY PROVIDING SELECTABLE VERTICAL AND LATERAL SEPARATION BETWEEN IPD
App. No. 12/042,903
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTERNAL INTERCONNECTS WITHIN A DIE PLATFORM
App. No. 12/036,056
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INTEGRATED CIRCUIT PACKAGE WITH IMPROVED CONNECTIONS
App. No. 11/965,621
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MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING INTERPOSER
App. No. 11/965,641
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE MODULE
App. No. 11/958,603
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE FOR ENCAPSULATED DIE HAVING PRE-APPLIED PROTECTIVE LAYER
App. No. 11/957,101
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING AND ANTI-FLASH STRUCTURE
App. No. 11/954,613
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION
App. No. 11/952,951
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BASE STRUCTURE DEVICE
App. No. 11/864,826
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME ARRAY
App. No. 11/862,406
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METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP
App. No. 11/858,554
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH LEADS
App. No. 11/854,934
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METHOD FOR DIRECTIONAL GRINDING ON BACKSIDE OF A SEMICONDUCTOR WAFER
App. No. 11/852,771
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH SIDE-BY-SIDE AND OFFSET STACKING
App. No. 11/849,087
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WIRE BONDING STRUCTURE AND METHOD THAT ELIMINATES SPECIAL WIRE BONDABLE FINISH AND REDUCES BONDING PITCH ON SUBSTRATES
App. No. 11/839,020
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLDING VENTS
App. No. 11/833,646
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICES
App. No. 11/833,898
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STACKABLE PACKAGE BY USING INTERNAL STACKING MODULES
App. No. 11/771,086
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANGING CONNECTION STACK
App. No. 11/769,512
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION
App. No. 11/768,640
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING
App. No. 11/766,787
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ULTRA THIN BUMPED WAFER WITH UNDER-FILM
App. No. 11/745,045
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE
App. No. 11/670,862
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STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/608,827
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INTEGRATED CIRCUIT SYSTEM WITH WAFER TRIMMING
App. No. 11/532,455
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STRUCTURE FOR BUMPED WAFER TEST
App. No. 11/464,726
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWN-SET DIE PAD AND METHOD OF MANUFACTURE THEREOF
App. No. 11/462,247
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STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE
App. No. 11/381,683
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EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/379,332
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INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG
App. No. 11/279,131
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE BOND PATTERN
App. No. 11/278,414
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NET SPACER
App. No. 11/278,411
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INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/276,727
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MULTI-CHIP PACKAGE SYSTEM
App. No. 11/326,211
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STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM
App. No. 11/255,740
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