IP Library Granted Patent US 7,897,502
Granted Patent B2
US 7,897,502 · App. 12/207,986 · Granted Mar 1, 2011

Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,897,502
App. No.
12/207,986
Granted
Mar 1, 2011
Kind
B2
Abstract

A method of making a semiconductor device comprises forming a first conductive layer recessed below a surface of a substrate. The method further comprises forming a second conductive layer raised above the surface of the substrate to create a vertical offset between the first and second conductive layers. The method further comprises forming an interconnect structure on the first and second conductive layers.

Claims (62)

1. A method of making a semiconductor device, comprising:

forming a first conductive layer extending above a surface of a carrier;

pressing the first conductive layer into a surface of a substrate so that the first conductive layer is recessed below the surface of the substrate;

removing the carrier after pressing the first conductive layer into the surface of the substrate;

forming a second conductive layer above the surface of the substrate to create a vertical offset between the first and second conductive layers; and

forming bond wire bumps on the first and second conductive layers.

2. The method of claim 1 , further including:

forming a via through the substrate; and

filling the via with conductive material.

3. The method of claim 1 , further including:

forming a seed layer over the carrier prior to forming the first conductive layer; and

removing the seed layer after forming the second conductive layer.

4. The method of claim 1 , wherein a height of the bond wire bumps is about 10 micrometers.

5. The method of claim 1 , wherein the vertical offset is about 20 micrometers.

6. A method of making a semiconductor device, comprising:

forming a first conductive layer extending above a surface of a carrier;

pressing the first conductive layer into a surface of a substrate so that the first conductive layer is recessed below the surface of the substrate;

removing the carrier after pressing the first conductive layer into the surface of the substrate;

forming a second conductive layer above the surface of the substrate to create a vertical offset between the first and second conductive layers; and

forming an interconnect structure on the first and second conductive layers.

7. The method of claim 6 , wherein the interconnect structure includes bond wire bumps, conductive posts, or solder bumps.

8. The method of claim 6 , further including:

forming a via through the substrate; and

filling the via with conductive material.

9. The method of claim 6 , further including:

forming a seed layer over the carrier prior to forming the first conductive layer; and

removing the seed layer after forming the second conductive layer.

10. The method of claim 6 , wherein a height of the interconnect structure is about 10 micrometers.

11. The method of claim 6 , wherein the vertical offset is about 20 micrometers.

12. A method of making a semiconductor device, comprising:

forming a first conductive layer recessed below a surface of a substrate;

forming a second conductive layer raised above the surface of the substrate to create a vertical offset between the first and second conductive layers; and

forming an interconnect structure on the first and second conductive layers.

13. The method of claim 12 , wherein the step of forming the first conductive layer includes:

forming a first conductive layer extending above a surface of a carrier; and

pressing the first conductive layer into the surface of the substrate so that the first conductive layer is recessed below the surface of the substrate.

14. The method of claim 13 , further including removing the carrier after pressing the first conductive layer into the surface of the substrate.

15. The method of claim 12 , wherein the interconnect structure includes bond wire bumps, conductive posts, or solder bumps.

16. The method of claim 12 , further including:

forming a via through the substrate; and

filling the via with conductive material.

17. The method of claim 12 , further including:

forming a seed layer over the carrier prior to forming the first conductive layer; and

removing the seed layer after forming the second conductive layer.

18. The method of claim 12 , wherein a height of the interconnect structure is about 10 micrometers.

19. The method of claim 12 , wherein the vertical offset is about 20 micrometers.

20. A method of making a semiconductor device, comprising:

forming a seed layer over a carrier prior to forming a first conductive layer;

forming the first conductive layer recessed below a surface of a substrate;

forming a second conductive layer raised above the surface of the substrate to create a vertical offset between the first and second conductive layers;

removing the seed layer after forming the second conductive layer; and

forming an interconnect structure on the first and second conductive layers.

21. The method of claim 20 , wherein the step of forming the first conductive layer includes:

forming the first conductive layer to extend above a surface of the carrier; and

pressing the first conductive layer into the surface of the substrate so that the first conductive layer is recessed below the surface of the substrate.

22. The method of claim 21 , further including removing the carrier after pressing the first conductive layer into the surface of the substrate.

23. The method of claim 20 , wherein the interconnect structure includes bond wire bumps, conductive posts, or solder bumps.

24. The method of claim 20 , further including:

forming a via through the substrate; and

filling the via with conductive material.

25. The method of claim 20 , wherein a height of the interconnect structure is about 10 micrometers.

26. The method of claim 20 , wherein the vertical offset is about 20 micrometers.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME. Recorded Sep 22, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065015/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 14, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064962/0123 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0292) Recorded Aug 30, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE.LTE.
Reel/Frame 064783/0896 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0292 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2008
From: JANG, KIYOUN; KIM, SUNGSOO; KANG, YONGHEE
To: STATS CHIPPAC, LTD.
Reel/Frame 021585/0134 →