Patent Assignment
Reel/Frame 064962/0123
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
Recorded: 2023-09-14
Received: 2023-09-19
Pages: 13
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(80)
METHOD FOR MAKING A STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE
App. No. 12/784,434
→
METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE WITH FINE PITCH LEAD FINGERS
App. No. 12/767,670
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING SHIELD
App. No. 12/762,602
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 12/730,171
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/722,759
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK AND METHOD OF MANUFACTURE THEREOF
App. No. 12/690,092
→
BONDING TOOL FOR MOUNTING SEMICONDUCTOR CHIPS
App. No. 12/635,536
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE USING SACRIFICIAL CARRIER
App. No. 12/615,428
→
STACKABLE MULTI-CHIP PACKAGE SYSTEM WITH SUPPORT STRUCTURE
App. No. 12/615,195
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
App. No. 12/572,568
→
STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
App. No. 12/571,234
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CIRCUITRY STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/562,722
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THROUGH SEMICONDUCTOR VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/562,702
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/557,481
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A TIERED SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/538,098
→
THROUGH-HOLE VIA ON SAW STREETS
App. No. 12/496,046
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/488,089
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECTION SUPPORT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/484,131
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST, AND METHOD OF MANUFACTURE THEREOF
App. No. 12/473,233
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 12/472,236
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING IPD STRUCTURE USING SMOOTH CONDUCTIVE LAYER AND BOTTOM-SIDE CONDUCTIVE LAYER
App. No. 12/472,170
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A 3D INDUCTOR FROM PREFABRICATED PILLAR FRAME
App. No. 12/467,908
→
MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING
App. No. 12/433,852
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/413,302
→
STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE
App. No. 12/409,489
→
LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
App. No. 12/398,806
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
App. No. 12/391,807
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CARRIER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/360,644
→
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING INTEGRATED PASSIVE DEVICES INTO THE PACKAGE ELECTRICALLY INTERCONNECTED USING CONDUCTIVE PILLARS
App. No. 12/331,698
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED TERMINAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/331,416
→
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/331,347
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 12/325,193
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT
App. No. 12/238,153
→
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
App. No. 12/237,276
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING
App. No. 12/237,291
→
SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD
App. No. 12/235,144
→
METHOD OF FORMING A WAFER LEVEL PACKAGE WITH RDL [[BUMP]] INTERCONNECTION OVER ENCAPSULANT BETWEEN BUMP AND SEMICONDUCTOR DIE
App. No. 12/235,000
→
METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 12/207,986
→
BALL GRID ARRAY PACKAGE STACKING SYSTEM
App. No. 12/206,383
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION
App. No. 12/201,896
→
A METHOD FOR FORMING AN ETCHED RECESS PACKAGE ON PACKAGE SYSTEM
App. No. 12/185,058
→
PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION
App. No. 12/171,890
→
SEMICONDUCTOR DEVICE AND METHOD OF SHUNT TEST MEASUREMENT FOR PASSIVE CIRCUITS
App. No. 12/167,039
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION
App. No. 12/146,411
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/146,135
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD
App. No. 12/128,116
→
WIREBONDLESS WAFER LEVEL PACKAGE WITH PLATED BUMPS AND INTERCONNECTS
App. No. 12/126,548
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT
App. No. 12/121,752
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RIGID LOCKING LEAD
App. No. 12/055,642
→
WAFER INTEGRATED WITH PERMANENT CARRIER AND METHOD THEREFOR
App. No. 12/055,171
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
App. No. 12/052,910
→
PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS
App. No. 12/051,625
→
PACKAGE-ON-PACKAGE SYSTEM WITH INTERNAL STACKING MODULE INTERPOSER
App. No. 12/051,280
→
BALL GRID ARRAY PACKAGE SYSTEM
App. No. 12/050,400
→
INTEGRATED CIRCUIT WITH STEP MOLDED INNER STACKING MODULE PACKAGE IN PACKAGE SYSTEM
App. No. 12/045,646
→
SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR DIE EACH HAVING IPD AND METHOD OF REDUCING MUTUAL INDUCTIVE COUPLING BY PROVIDING SELECTABLE VERTICAL AND LATERAL SEPARATION BETWEEN IPD
App. No. 12/042,903
→
INTEGRATED CIRCUIT PACKAGE WITH IMPROVED CONNECTIONS
App. No. 11/965,621
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD LOCKING STRUCTURE
App. No. 11/964,501
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION
App. No. 11/952,951
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BASE STRUCTURE DEVICE
App. No. 11/864,826
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME ARRAY
App. No. 11/862,406
→
SEMICONDUCTOR DIE WITH THROUGH-HOLE VIA ON SAW STREETS AND THROUGH-HOLE VIA IN ACTIVE AREA OF DIE
App. No. 11/861,251
→
METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP
App. No. 11/858,554
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH LEADS
App. No. 11/854,934
→
METHOD FOR DIRECTIONAL GRINDING ON BACKSIDE OF A SEMICONDUCTOR WAFER
App. No. 11/852,771
→
WIRE BONDING STRUCTURE AND METHOD THAT ELIMINATES SPECIAL WIRE BONDABLE FINISH AND REDUCES BONDING PITCH ON SUBSTRATES
App. No. 11/839,020
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLDING VENTS
App. No. 11/833,646
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICES
App. No. 11/833,898
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION
App. No. 11/768,640
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/558,589
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD STRUCTURES INCLUDING A DUMMY TIE BAR
App. No. 11/558,387
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PAD TO PAD BONDING
App. No. 11/536,242
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERLOCK
App. No. 11/466,748
→
STRUCTURE FOR BUMPED WAFER TEST
App. No. 11/464,726
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE BOND PATTERN
App. No. 11/278,414
→
WAFER LEVEL CHIP SCALE PACKAGE SYSTEM WITH A THERMAL DISSIPATION STRUCTURE
App. No. 11/276,611
→
INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING A NON-LEADED PACKAGE
App. No. 11/307,383
→
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE
App. No. 11/164,336
→
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS
App. No. 11/163,558
→
STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM
App. No. 11/255,740
→