IP Library Granted Patent US 7,875,967
Granted Patent B2
US 7,875,967 · App. 12/045,646 · Granted Jan 25, 2011

Integrated circuit with step molded inner stacking module package in package system

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Quick Facts
Patent No.
US 7,875,967
App. No.
12/045,646
Granted
Jan 25, 2011
Kind
B2
Abstract

An integrated circuit package system including: providing a substrate; mounting an integrated circuit above the substrate; mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step molded in the inner stacking module encapsulation, above the integrated circuit; and encapsulating the inner stacking module, and the integrated circuit with an encapsulation.

Claims (53)

1. A method for manufacturing an integrated circuit package in package system comprising:

providing a substrate;

mounting an integrated circuit above the substrate;

mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step, with a planar bottom surface, molded in the inner stacking module encapsulation containing an inner stacking module die larger than the molded integral step, above the integrated circuit; and

forming an encapsulation covering the inner stacking module, and the integrated circuit with the encapsulation between the planar bottom surface of the molded integral step and the integrated circuit.

2. The method as claimed in claim 1 wherein:

mounting the inner stacking module having the molded integral step includes having the molded integral step largely comprising one quadrant beneath the inner stacking module.

3. The method as claimed in claim 1 wherein:

mounting the inner stacking module having the molded integral step includes having the molded integral step largely comprising three quadrants beneath the inner stacking module.

4. The method as claimed in claim 1 further comprising:

mounting an epoxy between the integrated circuit and the molded integral step.

5. The method as claimed in claim 1 further comprising:

mounting a penetrable film adhesive between on the integrated circuit.

6. A method for manufacturing an integrated circuit package in package system comprising:

providing a substrate;

mounting an integrated circuit above the substrate;

mounting a wire-bonded die above the integrated circuit;

connecting the integrated circuit and the wire-bonded die to the substrate with a wire bond;

mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step, with a planar bottom surface, molded in the inner stacking module encapsulation containing an inner stacking module die larger than the molded integral step, above the integrated circuit; and

forming an encapsulation covering the inner stacking module, and the integrated circuit with the encapsulation between the planar bottom surface of the molded integral step and the integrated circuit.

7. The method as claimed in claim 6 further comprising:

mounting a penetrable film adhesive between the wire-bonded die and the inner stacking module.

8. The method as claimed in claim 6 further comprising:

mounting an epoxy between the wire-bonded die and the inner stacking module.

9. The method as claimed in claim 6 wherein:

mounting the inner stacking module having the molded integral step above the integrated circuit includes creating a gap between the integrated circuit and the inner stacking module and filling the gap with encapsulation.

10. The method as claimed in claim 6 wherein:

mounting an inner stacking module having a molded integral step above the integrated circuit includes creating a gap between the integrated circuit and the inner stacking module and the gap size is controlled by the molded integral step size.

11. An integrated circuit package in package system comprising:

a substrate;

an integrated circuit mounted above the substrate;

an inner stacking module, having an inner stacking module encapsulation and a molded integral step, with a planar bottom surface, molded in the inner stacking module encapsulation containing an inner stacking module die larger than the molded integral step, above the integrated circuit; and

an encapsulation covering the inner stacking module, and the integrated circuit with the encapsulation between the planar bottom surface of the molded integral step and the integrated circuit.

12. The system as claimed in claim 11 wherein:

the inner stacking module having the molded integral step includes having the molded integral step largely comprising one quadrant beneath the inner stacking module.

13. The system as claimed in claim 11 wherein:

the inner stacking module having the molded integral step includes having the molded integral step largely comprising three quadrants beneath the inner stacking module.

14. The system as claimed in claim 11 further comprising:

an epoxy mounted between the integrated circuit and the molded integral step.

15. The system as claimed in claim 11 further comprising:

a penetrable film adhesive on the integrated circuit.

16. The system as claimed in claim 11 further comprising:

a wire-bonded die mounted above the integrated circuit;

the integrated circuit and the wire-bonded die connected to the substrate with a wire bond; and

the wire-bonded die encapsulated by the encapsulation.

17. The system as claimed in claim 16 further comprising:

a penetrable film adhesive mounted between the wire-bonded die and the inner stacking module.

18. The system as claimed in claim 16 further comprising:

an epoxy mounted between the wire-bonded die and the inner stacking module.

19. The system as claimed in claim 16 further comprising:

a gap between the wire-bonded die and the inner stacking module filled with the encapsulation.

20. The system as claimed in claim 16 further comprising:

a gap between the wire-bonded die and the inner stacking module having the gap size controlled by the molded integral step size.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME. Recorded Sep 22, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065015/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 14, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064962/0123 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0292) Recorded Aug 30, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE.LTE.
Reel/Frame 064783/0896 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0292 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2008
From: YANG, DEOKKYUNG; YOON, IN SANG; CHUNG, JAE HAN
To: STATS CHIPPAC LTD.
Reel/Frame 020625/0993 →