Structure for bumped wafer test
A semiconductor package includes a substrate having a bond pad disposed on a top surface of the substrate. A first passivation layer is formed over the substrate and bond pad. The first passivation layer has an opening to expose the bond pad. An under bump metallurgy is formed over the first passivation layer. An end of the under bump metallurgy extends beyond an end of the bond pad. A second passivation layer is formed over the under bump metallurgy. The second passivation layer has a first opening to expose a first surface of the under bump metallurgy, and a second opening which is etched to expose a second surface of the under bump metallurgy. A solder ball is attached to the first surface of the under bump metallurgy to provide electrical connectivity. The second opening in the second passivation layer receives a probe needle to test the semiconductor device.
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate having a bond pad disposed on a top surface of the substrate;
forming a first passivation layer over the substrate and bond pad, the first passivation layer having an opening to expose the bond pad;
forming an under bump metallurgy over the first passivation layer, wherein a first portion of the under bump metallurgy is disposed over the bond pad and a second portion of the under bump metallurgy extends beyond an end of the bond pad, the first passivation layer having a first thickness over a portion of the substrate below the second portion of the under bump metallurgy and second thickness over the bond pad which is less than the first thickness;
forming a second passivation layer over the under bump metallurgy, the second passivation layer having a first opening to expose the first portion of the under bump metallization;
etching a second opening in the second passivation layer away from the first opening to expose the second portion of the under bump metallurgy while maintaining the second passivation layer around the first opening; and
connecting a test probe to the second portion of the under bump metallurgy to perform an electrical test.
2. The method of manufacturing of claim 1 , further including attaching a solder ball to the first surface of the under bump metallurgy to provide electrical connectivity.
3. The method of manufacturing of claim 2 , wherein the solder ball connects to a flip-chip semiconductor device.
4. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a bond pad over the substrate;
forming a first passivation layer over the substrate and bond pad;
removing a portion of the first passivation layer to expose the bond pad;
forming an under bump metallurgy (UBM) over the bond pad and first passivation layer, the UBM having a first portion over the bond pad and a second portion extending beyond the bond pad, the first passivation layer having a first thickness over a portion of the substrate below the second portion of the UBM and second thickness over the bond pad which is less than the first thickness;
forming a second passivation layer over the UBM and first passivation layer;
removing a first portion of the second passivation layer to form a first opening and expose the first portion of the UBM;
removing a second portion of the second passivation layer beyond the bond pad to form a second opening and expose the second portion of the UBM while maintaining the second passivation layer around the first opening;
forming a bump over the first portion of the UBM; and
connecting a test probe to the second portion of the UBM to perform an electrical test without contacting the bump.
5. The method of claim 4 , further including conforming the first portion of the UBM to the first passivation layer and bond pad.
6. The method of claim 4 , further including:
providing a semiconductor device; and
connecting the semiconductor device to the bump.
7. The method of claim 6 , wherein the semiconductor device is a flipchip type semiconductor device.
8. The method of claim 4 , wherein connecting the test probe to the second portion of the UBM avoids damage to the bump during the electrical test.
9. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a bond pad over the substrate;
forming a first passivation layer over the substrate and bond pad;
removing a portion of the first passivation layer to expose the bond pad;
forming an under bump metallurgy (UBM) over the bond pad and first passivation layer, the UBM having a first portion over the bond pad and a second portion extending beyond the bond pad, the first passivation layer having a first thickness over a portion of the substrate below the second portion of the UBM and second thickness over the bond pad which is less than the first thickness;
forming a second passivation layer over the UBM and first passivation layer;
removing a first portion of the second passivation layer to form a first opening and expose the first portion of the UBM; and
removing a second portion of the second passivation layer beyond the bond pad to form a second opening and expose the second portion of the UBM while maintaining the second passivation layer around the first opening.
10. The method of claim 9 , further including forming a bump over the first portion of the UBM.
11. The method of claim 10 , further including:
providing a semiconductor device; and
connecting the semiconductor device to the bump.
12. The method of claim 11 , wherein the semiconductor device is a flipchip type semiconductor device.
13. The method of claim 9 , further including connecting a test probe to the second portion of the UBM to perform an electrical test without contacting the bump.
14. The method of claim 13 , wherein connecting the test probe to the second portion of the UBM avoids damage to the bump during the electrical test.
15. The method of claim 9 , further including conforming the first portion of the UBM to the first passivation layer and bond pad.
16. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a bond pad over the substrate;
forming a first passivation layer over the substrate and bond pad;
forming an under bump metallurgy (UBM) over the bond pad and first passivation layer, wherein the UBM has a first portion over the bond pad and a second portion extending beyond the bond pad, the first passivation layer having a first thickness over a portion of the substrate below the second portion of the UBM and second thickness over the bond pad which is less than the first thickness;
forming a second passivation layer over the UBM and first passivation layer;
removing a first portion of the second passivation layer to form a first opening and expose the UBM; and
removing a second portion of the second passivation layer beyond the bond pad to form a second opening and expose the UBM while maintaining the second passivation layer around the first opening.
17. The method of claim 16 , further including forming a bump over the UBM.
18. The method of claim 17 , further including:
providing a semiconductor device; and
connecting the semiconductor device to the bump.
19. The method of claim 18 , wherein the semiconductor device is a flipchip type semiconductor device.
20. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a bond pad over the substrate;
forming a first passivation layer over the substrate and bond pad;
forming an under bump metallurgy (UBM) over the bond pad and first passivation layer;
forming a second passivation layer over the UBM and first passivation layer;
removing a first portion of the second passivation layer to form a first opening and expose the UBM;
removing a second portion of the second passivation layer beyond the bond pad to form a second opening and expose the UBM while maintaining the second passivation layer around the first opening; and
connecting a test probe through the second opening to the UBM to perform an electrical test without contacting the bump.
21. The method of claim 20 , wherein connecting the test probe through the second opening to the UBM avoids damage to the bump during the electrical test.
22. The method of claim 20 , further including conforming the UBM to the first passivation layer and bond pad.