Stackable multi-chip package system with support structure
A stackable multi-chip package system is provided including forming an external interconnect, having a base and a tip, and a paddle; mounting a first integrated circuit die over the paddle; stacking a second integrated circuit die over the first integrated circuit die in a active side to active side configuration; connecting the first integrated circuit die and the base; connecting the second integrated circuit die and the base; and molding the first integrated circuit die, the second integrated circuit die, the paddle, and the external interconnect with the external interconnect partially exposed.
1. A stackable multi-chip package system comprising:
external interconnects, wherein each of the external interconnects having a base and a tip;
a paddle;
a first integrated circuit die over the paddle;
a second integrated circuit die over the first integrated circuit die in an active side to active side configuration;
a first internal interconnect between the first integrated circuit die and an inner portion of the base connected to the first integrated circuit die;
a second internal interconnect between the second integrated circuit die and the inner portion of the base connected to the second integrated circuit die includes the external interconnect connected to the second integrated circuit die is in an inverted configuration to the external interconnect connected to the first integrated circuit die; and
an encapsulation to cover the first integrated circuit die, the second integrated circuit die, the paddle, and the external interconnect with the external interconnect partially exposed.
2. The system as claimed in claim 1 further comprising a first stackable multi-chip package system over a second stackable multi-chip package system.
3. The system as claimed in claim 1 further comprising:
a first stackable multi-chip package system over a substrate;
a second stackable multi-chip package system over the first stackable multi-chip package system; and
a package encapsulation to cover the first stackable multi-chip package system and the
second stackable multi-chip package system with the substrate.
4. The system as claimed in claim 1 wherein the second integrated circuit die over the first integrated circuit die in the face-to-face configuration has a second active side of the second integrated circuit die facing the first active side of the first integrated circuit die.
5. The system as claimed in claim 1 wherein:
the external interconnect is a L-shape external interconnect, having the base and the tip;
the paddle is a die-attach paddle;
the first integrated circuit die is on the paddle with an adhesive;
the second integrated circuit die over the first integrated circuit die is an offset and active side to active side configuration;
the interconnect, between the first integrated circuit die and the external interconnect, is to an inner portion of the base;
the interconnect, between the second integrated circuit die and the external interconnect, is to the inner portion of the base; and
the encapsulation is a cover for the first integrated circuit die and a partial cover for the second integrated circuit die, the paddle, and the external interconnect.
6. The system as claimed in claim 5 wherein the encapsulation is a cover for the first integrated circuit die and a partial cover for the second integrated circuit die, the paddle, and the external interconnect includes:
a second non-active side of the second integrated circuit die exposed; and
a side of the paddle opposite the first integrated circuit die exposed.
7. The system as claimed in claim 5 wherein the die-attach paddle is comprised of a conductive material having planar rigidity.
8. The system as claimed in claim 5 further comprising dual rows of lands with bases and tips exposed in alternating positions.
9. The system as claimed in claim 5 wherein the die-attach paddle is an electromagnetic interference shield.