IP Library Granted Patent US 7,915,716
Granted Patent B2
US 7,915,716 · App. 11/862,406 · Granted Mar 29, 2011

Integrated circuit package system with leadframe array

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,915,716
App. No.
11/862,406
Granted
Mar 29, 2011
Kind
B2
Abstract

An integrated circuit package system includes providing an integrated circuit die; attaching the integrated circuit die over a lead grid having lead blocks; and connecting a die interconnect to the integrated circuit die and the lead blocks.

Claims (34)

1. An integrated circuit package system comprising:

providing an integrated circuit die;

attaching the integrated circuit die over a lead grid having lead blocks and an interposer with the lead blocks extending below the interposer; and

connecting a die interconnect to the integrated circuit die and the lead blocks; and wherein a gap fill material fills a gap between the lead blocks and under a bottom surface of the interposer.

2. The system as claimed in claim 1 wherein connecting the die interconnect is between the integrated circuit die and the interposer.

3. The system as claimed in claim 1 further comprising attaching a lead interconnect to one of the lead blocks and another of the lead blocks.

4. The system as claimed in claim 1 further comprising attaching a lead interconnect to one of the lead blocks and an interposer.

5. An integrated circuit package system comprising:

providing an integrated circuit die;

attaching the integrated circuit die over a predetermined region of a lead grid having lead blocks and an interposer with the lead blocks extending below the interposer in a shape of rows and columns;

connecting a die interconnect to the integrated circuit die and the lead blocks adjacent the predetermined region;

applying an encapsulant over the die interconnect, the integrated circuit die, and the lead blocks; and

wherein a gap fill material fills a gap between the lead blocks and under a bottom surface of the interposer.

6. The system as claimed in claim 5 wherein providing the lead grid includes forming the lead blocks in a shape of substantially orthogonal rows and columns.

7. The system as claimed in claim 5 wherein providing the lead grid includes forming an interposer between the lead blocks.

8. The system as claimed in claim 5 further comprising attaching a lead interconnect to one of the lead blocks and another of the lead blocks in the predetermined region of the lead grid.

9. The system as claimed in claim 5 further comprising attaching a lead interconnect to one of the lead blocks and an interposer in the predetermined region of the lead grid.

10. An integrated circuit package system comprising:

an integrated circuit die;

a lead grid having lead blocks and an interposer with the integrated circuit die thereover and with the lead blocks extending below the interposer; and

a die interconnect connected to the integrated circuit die and the lead blocks; and

a gap fill material filling a gap between the lead blocks and under a bottom surface of the interposer.

11. The system as claimed in claim 10 wherein the die interconnect is between the integrated circuit die and the interposer.

12. The system as claimed in claim 10 further comprising a lead interconnect attached to one of the lead blocks and another of the lead blocks.

13. The system as claimed in claim 10 further comprising a lead interconnect attached to one of the lead blocks and an interposer.

14. The system as claimed in claim 10 wherein:

the integrated circuit die is over a predetermined region of the lead grid having the lead blocks in a shape of rows and columns;

the die interconnect is connected to the integrated circuit die and the lead blocks adjacent the predetermined region; and

further comprising:

an encapsulant over the die interconnect, the integrated circuit die, and the lead blocks.

15. The system as claimed in claim 14 wherein the lead grid includes the lead blocks in a shape of substantially orthogonal rows and columns.

16. The system as claimed in claim 14 wherein the lead grid includes an interposer between the lead blocks.

17. The system as claimed in claim 14 further comprising a lead interconnect attached to one of the lead blocks and another of the lead blocks in the predetermined region of the lead grid.

18. The system as claimed in claim 14 further comprising a lead interconnect attached to one of the lead blocks and an interposer in the predetermined region of the lead grid.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME. Recorded Sep 22, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065015/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 14, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064962/0123 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0292) Recorded Aug 30, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE.LTE.
Reel/Frame 064783/0896 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0292 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2007
From: PISIGAN, JAIRUS LEGASPI; PUNZALAN, JEFFREY D.; TAY, LIONEL CHIEN HUI; CAMACHO, ZIGMUND RAMIREZ
To: STATS CHIPPAC LTD.
Reel/Frame 019889/0402 →