Granted Patent B2

US 7,923,304 · App. 12/557,481 · Granted Apr 12, 2011

Abstract

Claims (16)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate including forming a passivation layer having a via, above the substrate;

filling the via of the passivation layer with the conductive pillar;

removing the passivation layer;

mounting an integrated circuit to the substrate beside the conductive pillar; and

encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond, including forming the encapsulation around the conductive pillar and leaving side portions of the conductive pillar exposed above the top surface of the encapsulation.

2. The method as claimed in claim 1 further comprising:

forming a second conductive pillar including forming a via through the encapsulation;

forming a second passivation layer on the top surface of the encapsulation;

filling the via with the conductive pillar beyond the top surface of the encapsulation; and

removing the second passivation layer to expose side portions of the conductive pillars above the encapsulation.

3. The method as claimed in claim 1 wherein:

mounting the integrated circuit includes mounting a flip-chip or a wire-bonded die.

4. The method as claimed in claim 1 further comprising:

depositing a solder paste atop the conductive pillar.

Assignments (8)