Multi-chip package system

1. A method for manufacturing a chip package system comprising:

providing a chip having interconnects provided thereon;

forming a molding compound on the chip and encapsulating the interconnects; and

forming a groove in the molding compound and the interconnects to expose the interconnects and the molding compound in a coplanar surface.

2. The method as claimed in claim 1 further comprising:

providing large interconnects on the chip that are larger than the interconnects;

forming the molding compound on the chip encapsulates the large interconnects; and

removing the molding compound above the large interconnects to expose the large interconnects.

3. The method as claimed in claim 1 further comprising:

providing a package board having wiring layers provided thereon; and

conductively connecting the interconnects to the wiring layers on the package board by the interconnects or by bond wires.

4. The method as claimed in claim 1 further comprising:

providing a package board having wiring layers provided thereon;

providing large interconnects on the chip that are larger than the interconnects;

forming the molding compound on the chip to encapsulate the large interconnects;

removing the molding compound above the large interconnects to expose the large interconnects; and

conductively connecting the interconnects to the wiring layers on the package board by the large interconnects or bond wires.

5. The method as claimed in claim 1 further comprising:

conductively connecting the interconnects on the chip to a second chip having small and large interconnects surrounded by the molding compound, the conductive connection at the small or large interconnects.

6. A method for manufacturing a chip package system comprising:

providing a wafer having interconnects provided thereon;

forming a molding compound on the wafer and encapsulating the interconnects;

forming a groove in the molding compound and the interconnects to expose the interconnects and the molding compound in a coplanar surface having evidence of being sawn; and

singulating the wafer to form first and second chip packages.

7. The method as claimed in claim 6 further comprising:

providing large interconnects on the wafer that are larger than the interconnects;

forming the molding compound on the wafer encapsulates the large interconnects;

removing the molding compound above the large interconnects to expose the large interconnects; and

the singulating the wafer forms third and fourth chip packages.

8. The method as claimed in claim 6 further comprising:

providing a package board having wiring layers provided thereon;

conductively connecting the interconnects to wiring layers on the package board by the interconnects, bond wires, or the first chip package through the second chip package.

9. The method as claimed in claim 6 further comprising:

providing a package board having wiring layers provided thereon;

providing small and large interconnects on a second wafer;

forming a second molding compound on the second wafer to encapsulate the small and large interconnects;

removing the second molding compound above the small and large interconnects to expose the small and large interconnects;

singulating the second wafer to form third and fourth chip packages; and

conductively connecting the interconnects of the first or third chip packages to the wiring layers on the package board by the interconnects, the small or large interconnects, bond wires, or through the second or fourth chip packages.

10. The method as claimed in claim 6 further comprising:

providing small and large interconnects on a second wafer;

forming a second molding compound on the second wafer to encapsulate the small and large interconnects;

removing the second molding compound above the small and large interconnects to expose the small and large interconnects;

singulating the second wafer to form third and fourth chip packages; and

conductively connecting two of the first, second, third, or fourth chip packages.

11. A chip package system comprising:

a chip having interconnects provided on the top thereof; and

a molding compound on the chip around the interconnects and having a groove in the top thereof includes the tops of the interconnects cut to be coplanar with the molding compound.

12. The system as claimed in claim 11 further comprising:

large interconnects on the chip that are larger than the interconnects; and

the molding compound on the chip around the large interconnects and exposing the tops of the large interconnects at the top of the molding compound.

13. The system as claimed in claim 11 further comprising:

a package board having wiring layers provided thereon; and

the interconnects conductively connected to the wiring layers on the package board by the interconnects or by bond wires.

14. The system as claimed in claim 11 further comprising:

a package board having wiring layers provided thereon;

large interconnects on the chip that are larger than the interconnects;

the molding compound on the chip around the large interconnects and exposing the tops of the large interconnects at the top of the molding compound; and

the interconnects and the large interconnects conductively connected to the wiring layers on the package board by the interconnects, the large interconnects, or bond wires.

15. The system as claimed in claim 11 further comprising:

the interconnects on the chip conductively connected to a second chip having small and large interconnects surrounded by the molding compound, the conductive connection at the small or large interconnects.

16. A chip package system comprising:

first and second chip packages characterized by being from the same wafer covered by a single molding compound; and

the first and second chip packages each comprises:

a chip having interconnects provided thereon, and

the molding compound on the chip around the interconnects and having a groove in the top thereof to includes the tops of the interconnects cut to be coplanar with the molding compound.

17. The system as claimed in claim 16 further comprising:

third and fourth chip packages characterized by being formed from the same wafer and covered by the single molding compound; and

the third and fourth chip packages each comprises:

a chip having large interconnects that are larger than the interconnects, and

the molding compound on the chip is around the large interconnects to expose the top of the large interconnects.

18. The system as claimed in claim 16 further comprising:

a package board having wiring layers provided thereon; and

the interconnects are conductively connected to wiring layers on the package board by the interconnects, bond wires, or the first chip package through the second chip package.

19. The system as claimed in claim 16 further comprising:

a package board having wiring layers provided thereon;

third and fourth chip packages wherein each chip package comprises:

a chip having large interconnects that are larger than the interconnects, and

a molding compound on the chip around the large interconnects and exposing the top of the large interconnects; and

the interconnects of the first or third chip packages conductively connected to the wiring layers on the package board by the interconnects, the small or large interconnects, bond wires, or through the second or fourth chip packages.

20. The system as claimed in claim 16 further comprising:

third and fourth chip packages wherein each chip package comprises:

a chip having large interconnects that are larger than the interconnects;

a molding compound on the chip around the large interconnects and exposing the top of the large interconnects; and

two of the first, second, third, or fourth chip packages are conductively connected.