IP Library Granted Patent US 7,863,100
Granted Patent B2
US 7,863,100 · App. 12/408,662 · Granted Jan 4, 2011

Integrated circuit packaging system with layered packaging and method of manufacture thereof

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 7,863,100
App. No.
12/408,662
Granted
Jan 4, 2011
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.

Claims (52)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a base package having a base interposer;

forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound and the intermediate package embedded link trace is not in touch with the intermediate interposer;

forming a cap package having a cap interposer; and

connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.

2. The method as claimed in claim 1 wherein forming the base package includes forming a first type base package having an interconnecting contact extension and an edge interconnecting contact extension attached to a top surface of the base interposer and a base package contact extension attached to a bottom surface of the base interposer.

3. The method as claimed in claim 1 wherein forming the intermediate package includes forming a first type intermediate package having the intermediate package embedded link trace encapsulated in the intermediate package mold compound, the top and bottom surface of the intermediate package embedded link trace being exposed and not encapsulated.

4. The method as claimed in claim 1 wherein forming the base package includes forming a second type base package having a base package contact extension attached to a bottom surface of the base interposer.

5. The method as claimed in claim 1 wherein forming the intermediate package includes forming a second type intermediate package having an interconnecting contact extension attached to the bottom surface of the intermediate interposer and an edge interconnecting contact extension attached to the bottom surface of the intermediate package embedded link trace.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming a base package having a base interposer and a semiconductor chip, the semiconductor chip being encapsulated in a base package mold compound;

forming an intermediate package having an intermediate interposer, a semiconductor chip; and an intermediate package embedded link trace, the semiconductor chip and the intermediate package embedded link trace being encapsulated in an intermediate package mold compound and the intermediate package embedded link trace is not in touch with the intermediate interposer;

forming a cap package having a cap interposer and a semiconductor chip, the semiconductor chip being encapsulated in a cap package mold compound; and

connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.

7. The method as claimed in claim 6 wherein connecting the intermediate package to the cap package includes:

attaching a cap package contact extension to the cap interposer; and

connecting the cap package contact extension to the intermediate package embedded link trace.

8. The method as claimed in claim 6 further comprising:

connecting the intermediate interposer and the base interposer using an interconnecting contact extension.

9. The method as claimed in claim 6 wherein forming the intermediate package includes:

attaching the intermediate interposer to a contact metal trace through an edge bar;

attaching an intermediate package first die to the intermediate interposer;

attaching an intermediate package second die to the intermediate package first die;

connecting the intermediate package second die and the intermediate package first die to an intermediate bonding pad on the intermediate interposer through an intermediate bonding wire;

attaching the intermediate package embedded link trace to the contact metal trace;

encapsulating the intermediate package second die, the intermediate package first die, the intermediate bonding wire, and the intermediate package embedded link trace in the intermediate package mold compound; and

removing the contact metal trace.

10. The method as claimed in claim 6 wherein forming the intermediate package includes:

attaching the intermediate interposer to a contact tape;

attaching an intermediate package first die to the intermediate interposer;

attaching an intermediate package second die to the intermediate package first die;

connecting the intermediate package second die and the intermediate package first die to an intermediate bonding pad on the intermediate interposer through an intermediate bonding wire;

attaching the intermediate package embedded link trace to the contact tape;

encapsulating the intermediate package second die, the intermediate package first die, the intermediate bonding wire, and the intermediate package embedded link trace in the intermediate package mold compound; and

removing the contact tape.

11. An integrated circuit packaging system comprising:

a base package having a base interposer;

a cap package having a cap interposer; and

an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound and the intermediate package embedded link trace is not in touch with the intermediate interposer and, the intermediate package being connected to the cap package and the base package through the intermediate package embedded link trace.

12. The system as claimed in claim 11 wherein the base package is a first type base package having an interconnecting contact extension and an edge interconnecting contact extension attached to a top surface of the base interposer and a base package contact extension attached to a bottom surface of the base interposer.

13. The system as claimed in claim 11 wherein the intermediate package is a first type intermediate package having the intermediate package embedded link trace encapsulated in the intermediate package mold compound, the top and bottom surface of the intermediate package embedded link trace being exposed and not encapsulated.

14. The system as claimed in claim 11 wherein the base package is a second type base package having a base package contact extension attached to a bottom surface of the base interposer.

15. The system as claimed in claim 11 wherein the intermediate package is a second type intermediate package having an interconnecting contact extension attached to the bottom surface of the intermediate interposer and an edge interconnecting contact extension attached to the bottom surface of the intermediate package embedded link trace.

16. The system as claimed in claim 11 further comprising:

a semiconductor chip encapsulated in a cap package mold compound in the cap package;

a semiconductor chip encapsulated in an intermediate package mold compound in the intermediate package; and

a semiconductor chip encapsulated in a base package mold compound in the base package.

17. The system as claimed in claim 16 further comprising:

a cap package contact extension connecting the bottom surface of the cap interposer to the intermediate package embedded link trace.

18. The system as claimed in claim 16 wherein the intermediate package embedded link trace is an embedded solder ball.

19. The system as claimed in claim 16 wherein the interconnecting contact extension, the edge interconnecting contact extension, the cap package contact extension, and the base package contact extension, are solder balls.

20. The system as claimed in claim 16 wherein the cap interposer, the intermediate interposer, and the base interposer are laminated substrates.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0309. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 11, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0767 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0309 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2009
From: YANG, JOUNGIN; JUNG, DONGJIN; PARK, DONGSAM
To: STATS CHIPPAC LTD.
Reel/Frame 022457/0007 →
Continuity (1)
Related Publication 20100237482A1 · Sep 23, 2010