IP Library Granted Patent US 7,763,963
Granted Patent B2
US 7,763,963 · App. 11/381,683 · Granted Jul 27, 2010

Stacked package semiconductor module having packages stacked in a cavity in the module substrate

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Quick Facts
Patent No.
US 7,763,963
App. No.
11/381,683
Granted
Jul 27, 2010
Kind
B2
Abstract

A stacked die chip scale package, in which a stacked die assembly is mounted within a cavity in a module substrate. In some embodiments certain of the die are stacked on a front side of a stacked die assembly substrate, and the stacked die assembly substrate is inverted in the cavity and the substrate is electrically interconnected to a front side of the module substrate; others of the die are stacked on the back side of the stacked die assembly substrate, and are interconnected by wire bonds to the front side of the module substrate. In some embodiments, the cavity is covered by a heat sink, and the stacked die assembly is mounted onto the heat sink. Also, methods for making the module are provided.

Claims (47)

1. A stacked die module comprising:

a module substrate including a dielectric layer having a cavity and a support in direct contact with the dielectric layer outside the cavity; and

a stacked die assembly having a first die mounted over and electrically connected to a front side of an assembly substrate, the stacked die assembly is inverted, mounted to and directly supported by the support within the cavity and is electrically connected to a front side of the module substrate.

2. The module of claim 1 , further comprising a first additional die mounted over a back side of the assembly substrate, and electrically connected to a front side of the module substrate.

3. The module of claim 1 , further comprising a first additional die mounted over and electrically connected to a back side of the assembly substrate.

4. The module of claim 1 wherein the first die is mounted by flip chip interconnection to the front side of the assembly substrate.

5. The module of claim 1 wherein the first die is electrically connected to the front side of the assembly substrate by wire bonding.

6. The module of claim 1 , further comprising at least a second die mounted over the first die and electrically connected by wire bonding to the front side of the assembly substrate.

7. The module of claim 3 , further comprising at least a second die mounted over the first die and electrically connected by wire bonding to a front side of the module substrate.

8. The module of claim 4 , further comprising at least a second die mounted over the first die, and electrically connected by wire bonding to a front side of the module substrate.

9. The module of claim 1 , wherein the cavity comprises an opening through the module substrate and the support spanning the opening at the back side of the module substrate.

10. The module of claim 9 wherein the stacked die assembly comprises a first die mounted over and connected by electrical interconnects to a front side of an assembly substrate, wherein the first die and the front side of the assembly substrate and electrical interconnects are enclosed in an encapsulation, wherein the stacked die assembly is affixed within the cavity to a surface of the support, and wherein the assembly substrate is electrically connected by wire bonding to a front side of the module substrate.

11. The module of claim 9 wherein the support comprises metal.

12. The module of claim 11 wherein the support comprises an electrically conductive metal.

13. The module of claim 9 wherein the support covers the opening.

14. The module of claim 9 wherein the support comprises a heat sink.

15. The module of claim 9 wherein the support comprises an electromagnetic shield.

16. A multi-chip module, comprising:

a stacked die assembly comprising

an assembly substrate having a front side and a back side and having at least a first die mounted onto and electrically connected to the front side, the assembly substrate and the first die constituting an assembly package; and

at least a first additional die mounted onto the back side of the assembly substrate; and

a module substrate having a front side and a back side, the module substrate including a dielectric layer having an opening and a support in direct contact with the dielectric layer outside the opening, the module substrate having the opening therethrough having a length and width at least sufficient to accommodate a length and width of the assembly package;

wherein the stacked die assembly is situated so that at least part of the assembly package is inverted and mounted to and directly supported by the support within the opening.

17. The module of claim 16 wherein the first die in the assembly package is connected to the assembly substrate by wire bonding.

18. The module of claim 16 wherein the first die in the assembly package is mounted by flip chip interconnect to the assembly package.

19. The module of claim 16 wherein the first additional die is electrically connected to the module substrate by wire bonding.

20. The module of claim 16 wherein the first additional die is mounted by flip chip interconnection to the stacked die assembly substrate.

21. The module of claim 16 wherein at least a second die is mounted over the first die in the assembly package, and is electrically connected to the module substrate by wire bonding.

22. The module of claim 16 wherein at least a second additional die is mounted over the first additional die in the assembly package, and is electrically connected to the module substrate by wire bonding.

23. The module of claim 16 wherein the die and interconnects on the front side of the stacked die assembly substrate are enclosed in an encapsulation.

24. The module of claim 16 wherein the die and interconnects on the front side of the stacked die assembly substrate are enclosed in a molding.

25. The module of claim 16 wherein the support spans the opening in the module substrate.

26. The module of claim 25 wherein a top surface of the assembly package is affixed to a surface of the support.

27. The module of claim 25 wherein the die and interconnects on the front side of the stacked die assembly substrate are enclosed in an encapsulation, and wherein a top surface of the encapsulation is affixed to a surface of the support.

28. The module of claim 25 wherein the die and interconnects on the front side of the stacked die assembly substrate are enclosed in a molding, and wherein a top surface of the molding is affixed to a surface of the support.

29. A semiconductor multi-chip module substrate comprising:

a dielectric layer and at least one patterned metal layer and having a front side and a back side formed into a substrate, the substrate having an opening therethrough and a support directly on the dielectric layer around the opening, the opening having a length and width sufficient at least to accommodate a footprint of a selected semiconductor package; and

a stacked die assembly having a first die mounted over and electrically connected to a front side of an assembly substrate, the stacked die assembly is inverted, mounted to and directly supported by the support within the opening and is electrically connected to a front side of the module substrate.

30. The module of claim 29 wherein the substrate comprises a two-metal layer substrate.

31. The module of claim 29 wherein the support spans the opening at the back side.

32. The module of claim 31 wherein the support covers the opening.

33. The module of claim 31 wherein the support comprises a metal sheet.

34. The module of claim 33 wherein the support comprises an electrically conductive metal.

35. The module of claim 33 wherein the support is connected to a reference electrical potential.

36. A computer including the semiconductor module of claim 1 , electrically connected to underlying circuitry in the computer.

37. A portable device including the semiconductor module of claim 1 , electrically connected to underlying circuitry in the portable device.

38. A telecommunications device including the semiconductor module of claim 1 , electrically connected to underlying circuitry in the telecommunications device.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0309. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 11, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0767 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0309 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 2ND PG OF ASSIGNMENT (PREVIOUSLY SUBMITTED 2ND PG OF DECLARATION IN ERROR AS 2ND PG OF ASSIGN) PREVIOUSLY RECORDED ON REEL 017662 FRAME 0482. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 3, 2008
From: HONG, SUNGMIN
To: STATS CHIPPAC LTD.
Reel/Frame 020321/0268 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2006
From: HONG, SUNGMIN
To: STATS CHIPPAC LTD.
Reel/Frame 017662/0482 →