Stacked die semiconductor device having circuit tape
View Patent ↗A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.
1. A semiconductor device, comprising:
a first integrated circuit chip;
a first circuit tape coupled to the first integrated circuit chip;
a second integrated circuit chip coupled to the first circuit tape; and
at least one component coupled to the first circuit tape.
2. The semiconductor device of claim 1 , wherein the at least one component comprises at least one passive component.
3. The semiconductor device of claim 1 , wherein the at least one component comprises at least one active component.
4. The semiconductor device of claim 1 , wherein the at least one component comprises at least one passive component and at least one active component.
5. The semiconductor device of claim 1 , wherein a bottom surface of the first integrated circuit chip is coupled to a substrate and the first circuit tape is coupled to a top surface of the first integrated circuit chip opposite the bottom surface.
6. The semiconductor device of claim 1 , wherein the second integrated circuit chip is coupled to a top surface of the first circuit tape.
7. The semiconductor device of claim 1 , wherein the at least one component coupled to the first circuit tape is coupled to a top surface of the first circuit tape.
8. The semiconductor device of claim 1 , wherein the first integrated circuit chip has a surface area smaller than a surface area of the second integrated circuit chip.
9. The semiconductor device of claim 1 , wherein the first integrated circuit chip has a surface area larger than a surface area of the second integrated circuit chip.
10. The semiconductor device of claim 1 , wherein the first integrated circuit chip has a surface area substantially similar to a surface area of the second integrated circuit chip.
11. The semiconductor device of claim 1 , further comprising a first encapsulant.