IP Library Granted Patent US 7,772,683
Granted Patent B2
US 7,772,683 · App. 11/608,827 · Granted Aug 10, 2010

Stacked integrated circuit package-in-package system

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 7,772,683
App. No.
11/608,827
Granted
Aug 10, 2010
Kind
B2
Abstract

A stacked integrated circuit package-in-package system is provided including forming a substrate having a top surface and a bottom surface, mounting a first device over the top surface, stacking a second device over the first device in an offset configuration, connecting a first internal interconnect between the first device and the bottom surface, connecting a second internal interconnect between the second device and the bottom surface, and encapsulating the first device and the second device.

Claims (58)

1. A stacked integrated circuit package-in-package system comprising:

forming a substrate having a top surface, a bottom surface, a first recess, and a second recess;

mounting a first device over the top surface;

stacking a second device over the first device in an offset configuration;

connecting a first internal interconnect between the first device and the bottom surface with the first internal interconnect around the first recess;

connecting a second internal interconnect between the second device and the bottom surface with the second internal interconnect around the second recess; and

encapsulating the first device and the second device.

2. The system as claimed in claim 1 wherein:

forming the substrate includes:

forming a first opening and a second opening in the substrate;

connecting the first internal interconnect between the first device and the bottom surface also includes:

connecting the first device and the bottom surface with the first internal interconnect through the first opening; and

connecting the second internal interconnect between the second device and the bottom surface further includes:

connecting the second device and the bottom surface with the second internal interconnect through the second opening.

3. The system as claimed in claim 1 further comprising forming the first device having a first integrated circuit die in a device encapsulation.

4. The system as claimed in claim 1 further comprising forming the first device having a stiffener in a device encapsulation.

5. A stacked integrated circuit package-in-package system comprising:

forming a laminate substrate having a top surface, a bottom surface with a bottom contact at the bottom surface, a first recess, and a second recess;

mounting a first device having a first integrated circuit die over the top surface;

stacking a second device having a second integrated circuit die over the first device in an offset configuration;

connecting a first internal interconnect between the first device and the bottom contact;

connecting a second internal interconnect between the second device and the bottom contact; and

encapsulating the first device, the second device, the first recess, and the second recess over the top surface.

6. The system as claimed in claim 5 wherein:

forming the laminate substrate includes:

forming a first opening and a second opening in the laminate substrate; and

encapsulating the first device and the second device also includes:

filling the first opening, and the second opening.

7. The system as claimed in claim 5 further comprising attaching an external interconnect to the bottom contact.

8. The system as claimed in claim 5 wherein forming the laminate substrate includes forming a first opening and a second opening having an opening width ranging from hundreds to two thousand of micrometers in the laminate substrate.

9. A stacked integrated circuit package-in-package system comprising:

a substrate having a top surface, a bottom surface, a first recess, and a second recess;

a first device over the top surface;

a second device over the first device in an offset configuration;

a first internal interconnect between the first device and the bottom surface with the first internal interconnect around the first recess;

a second internal interconnect between the second device and the bottom surface with the second internal interconnect around the second recess; and

a package encapsulation to cover the first device and the second device.

10. The system as claimed in claim 9 wherein:

the substrate has a first opening and a second opening;

the first internal interconnect is in the first opening; and

the second internal interconnect is in the second opening.

11. The system as claimed in claim 9 wherein the first device has a first integrated circuit die in a device encapsulation.

12. The system as claimed in claim 9 wherein the first device has a stiffener in a device encapsulation.

13. The system as claimed in claim 9 wherein:

the substrate is a laminate substrate having the top surface and the bottom surface with the bottom surface having a bottom contact;

the first device has a first integrated circuit die over the top surface;

the second device has a second integrated circuit die over the first device in an offset configuration;

the first internal interconnect is a bond wire between the first device with the bottom contact;

the second internal interconnect is the bond wire between the second device with the bottom contact; and

the package encapsulation is a cover for the first device, the second device, and the top surface.

14. The system as claimed in claim 13 wherein:

the laminate substrate has a first opening and a second opening; and

the package encapsulation is in the first opening, and the second opening.

15. The system as claimed in claim 13 wherein:

the laminate substrate has a first recess and a second recess; and

the package encapsulation is in the first recess, and the second recess.

16. The system as claimed in claim 13 further comprising an external interconnect attached to the bottom contact.

17. The system as claimed in claim 13 wherein the laminate substrate has a first opening and a second opening having an opening width ranging from hundreds to two thousand of micrometers.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0309. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 11, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0767 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0309 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2006
From: JANG, KI YOUN; HA, JONG-WOO; JU, JONG WOOK
To: STATS CHIPPAC LTD.
Reel/Frame 018607/0170 →
Continuity (1)
Related Publication 20080136006A1 · Jun 12, 2008