Leaded stacked packages having elevated die paddle
View Patent ↗A semiconductor package includes a leadframe, an elevated die paddle disposed above the leadframe, a first die attached to a lower surface of the elevated die paddle to support the first die within the semiconductor package, and a second die attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having a lower lead and an elevated die paddle structure, attaching a first die to the elevated die paddle structure with a die adhesive (DA) for supporting the first die within the semiconductor package, and wire bonding the first die to the lower lead.
1. A method of making a semiconductor package, comprising:
providing a leadframe;
providing a die paddle which is elevated above the leadframe, the die paddle having an opening formed through a central area of the die paddle;
mounting a first die to the die paddle over the opening to support the first die within the semiconductor package;
mounting a second die within the opening; and
electrically connecting the first die to the second die.
2. The method of claim 1 , further including forming an encapsulant over a portion of first die and die paddle.
3. The method of claim 1 , further including electrically connecting the first die to the second die with a ball grid array or wire bond.
4. The method of claim 1 , further including disposing an underfill material between the first die and second die for structural support.
5. The method of claim 1 , wherein the second die includes a leaded package, nonleaded package, array package, flip chip die, or passive component.
6. A method of making a semiconductor package, comprising:
providing a leadframe having an elevated die paddle disposed above the leadframe;
mounting a first die to the elevated die paddle for structural support;
electrically connecting a second die to the first die; and
disposing an underfill material between the first die and second die.
7. The method of claim 6 , further including forming an encapsulant over a portion of the first die for structural support.
8. The method of claim 6 , further including mounting the first die to the elevated die paddle with a die adhesive.
9. The method of claim 6 , wherein the second die includes a leaded package, nonleaded package, array package, flip chip die, or passive component.
10. A method of making a semiconductor package, comprising:
providing a leadframe disposed in a first plane;
providing a die paddle which is elevated above the leadframe in a second plane which is parallel to the first plane;
providing a plurality of die paddle supports coupled between the leadframe and die paddle;
mounting a first die to the die paddle to support the first die within the semiconductor package; and
attaching a second die to the first die.
11. The method of claim 10 , further including forming an encapsulant over a portion of first die and die paddle.
12. The method of claim 10 , further including disposing an underfill material between the first die and second die for structural support.
13. The method of claim 10 , wherein the second die includes a leaded package, nonleaded package, array package, flip chip die, or passive component.
14. The method of claim 10 , further including forming an opening through the central area of the die paddle, the first die being mounted over the opening to support the first die within the semiconductor package, the second die being disposed within the opening.
15. The method of claim 14 , further including mounting the second die within the opening using a ball grid array or wire bond.
16. A method of making a semiconductor package, comprising:
providing a leadframe disposed in a first plane;
providing an elevated die paddle disposed above the leadframe in a second plane which is parallel to the first plane;
mounting a first surface of a first die to the elevated die paddle to support the first die within the semiconductor package, the first die having a second surface disposed in the first plane of the leadframe; and
mounting a second die to the first surface of the first die.
17. The method of claim 16 , wherein the second die includes a leaded package, nonleaded package, array package, flip chip die, or passive component.
18. The method of claim 16 , further including forming an encapsulant over a portion of the elevated die paddle for structural support.
19. The method of claim 16 , further including disposing an underfill material between the first die and second die for structural support.
20. The method of claim 16 , further including forming an opening through the central area of the die paddle, the first die being mounted over the opening to support the first die within the semiconductor package, the second die being disposed within the opening.
21. The method of claim 20 , further including mounting the second die within the opening using a ball grid array or wire bond.