Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a silicon substrate having circuitry in a circuitry layer;

creating a partial via through the circuitry in the circuitry layer;

filling the partial via with a plug having a bottom surface;

creating a recess that is angled outward and exposes the bottom surface of the plug; and

coating the recess with a recess-insulation-layer while leaving the bottom surface of the plug exposed.

2. The method as claimed in claim 1 further comprising:

lining the partial via with a via-insulation-layer; and

wherein:

creating the recess includes creating the recess through the via-insulation-layer.

3. The method as claimed in claim 1 further comprising:

creating a plated contact inside the recess and the plated contact connects to the bottom surface of the plug.

4. The method as claimed in claim 1 further comprising:

creating a planar surface on the plug; and

creating a face-side-dielectric-layer surrounding the plug, while leaving the planar surface on the plug exposed.

5. The method as claimed in claim 1 wherein:

providing the silicon substrate includes providing a contact pad; and

creating the partial via includes creating the partial via through the contact pad.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a silicon substrate having circuitry in a circuitry layer;

creating a partial via through the circuitry in the circuitry layer;

filling the partial via with a plug having a bottom surface;

creating a recess that is angled outward and exposes the bottom surface of the plug;

coating the recess with a recess-insulation-layer while leaving the bottom surface of the plug exposed to create a through-silicon-via-die;

connecting the silicon substrate to a substrate; and

encapsulating the silicon substrate with an encapsulation.

7. The method as claimed in claim 6 further comprising:

mounting the silicon substrate over the substrate with the recess facing toward the substrate, mounting the silicon substrate over the substrate with the recess facing away from the substrate, mounting the silicon substrate in a substrate cavity, or a combination thereof.

8. The method as claimed in claim 6 further comprising:

mounting a second-through-silicon-via-die above the first-through-silicon-via-die.

9. The method as claimed in claim 6 wherein:

encapsulating includes partially encapsulating the through-silicon-via-die to expose the planar surface on the plug, the bottom surface of the plug, a plated contact created inside the recess, or a combination thereof.

10. The method as claimed in claim 6 further comprising:

mounting an integrated circuit structure above the through-silicon-via-die; and

connecting the integrated circuit structure to the through-silicon-via-die with an interconnect.

11. An integrated circuit packaging system comprising:

a silicon substrate having circuitry in a circuitry layer;

a partial via created through the circuitry in the circuitry layer;

a plug having a bottom surface that fills the partial via;

a recess that is angled outward and exposes the bottom surface of the plug; and

a recess-insulation-layer that coats the recess while leaving the bottom surface of the plug exposed.

12. The system as claimed in claim 11 further comprising:

a via-insulation-layer that lines the partial via; and

wherein:

the recess is created through the via-insulation-layer.

13. The system as claimed in claim 11 further comprising:

a plated contact inside the recess and the plated contact connects to the bottom surface of the plug.

14. The system as claimed in claim 11 further comprising:

creating a planar surface on the plug; and

creating a face-side-dielectric-layer surrounding the plug, while leaving the planar surface on the plug exposed.

15. The system as claimed in claim 11 further comprising:

a contact pad on the silicon substrate; and

wherein:

the partial via is created through the contact pad.

16. The system as claimed in claim 11 further comprising:

a substrate connected to the silicon substrate; and

an encapsulation that encapsulates the silicon substrate.

17. The system as claimed in claim 16 wherein:

the silicon substrate is mounted over the substrate with the recess facing toward the substrate, the silicon substrate is mounted over the substrate with the recess facing away from the substrate, the silicon substrate is mounted in a substrate cavity, or a combination thereof.

18. The system as claimed in claim 16 further comprising:

a second-through-silicon-via-die mounted above the first-through-silicon-via-die.

19. The system as claimed in claim 16 wherein:

the encapsulation partially encapsulates the through-silicon-via-die to expose the planar surface on the plug, the bottom surface of the plug, a plated contact created inside the recess, or a combination thereof.

20. The system as claimed in claim 16 further comprising:

an integrated circuit structure mounted above the through-silicon-via-die; and

the integrated circuit structure connected to the through-silicon-via-die with an interconnect.