Semiconductor package having through-hole vias on saw streets formed with partial saw

1. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of the plurality of die, the semiconductor wafer having a saw street between the plurality of die;

forming a trench in the saw street extending partially through the semiconductor wafer, a portion of the saw street below the trench having sufficient thickness to maintain structural support for the semiconductor wafer during processing steps of:

(a) forming metal vias in the trench of the saw street, and

(b) electrically connecting the metal vias to the contact pads;

removing the portion of the saw street below the trench along a backside of the semiconductor wafer; and

singulating the semiconductor wafer along the saw street to separate the plurality of die.

2. The method of claim 1 , further including:

filling the trench with organic material;

forming a plurality of vias in the organic material;

forming traces between the contact pads and plurality of vias; and

depositing conductive material in the plurality of vias to form the metal vias.

3. The method of claim 1 , wherein forming metal vias includes forming one metal via between the contact pads on adjacent die.

4. The method of claim 1 , wherein the semiconductor wafer is singulated through the metal vias to form half metal vias.

5. The method of claim 1 , wherein forming metal vias includes forming two metal vias side by side between the contact pads on adjacent die.

6. The method of claim 5 , wherein the semiconductor wafer is singulated along the saw street between the two metal vias to form full metal vias.

7. The method of claim 1 , wherein the trench is centered about the saw street.

8. The method of claim 1 , further including:

stacking the plurality of die to provide stacked die; and

electrically connecting the stacked die through the metal vias.

9. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of the plurality of die, the semiconductor wafer having a saw street between the plurality of die;

forming a trench in the saw street without using support material to support the semiconductor wafer, the trench extending partially through the semiconductor wafer, a portion of the saw street below the trench along a backside of the semiconductor wafer having sufficient thickness to maintain structural support for the semiconductor wafer without support material during processing steps of:

(a) forming conductive vias between the plurality of die, and

(b) electrically connecting the conductive vias to the contact pads;

removing the portion of the saw street below the trench along a backside of the semiconductor wafer; and

singulating the semiconductor wafer along the saw street to separate the plurality of die.

10. The method of claim 9 , further including:

filling the trench with organic material;

forming a plurality of vias in the organic material;

forming traces between the contact pads and plurality of vias; and

depositing conductive material in the plurality of vias to form the conductive vias.

11. The method of claim 9 , wherein forming conductive vias includes forming one conductive via between the contact pads on adjacent die.

12. The method of claim 9 , wherein the semiconductor wafer is singulated through the conductive vias to form half conductive vias.

13. The method of claim 9 , wherein forming conductive vias includes forming two conductive vias side by side between the contact pads on adjacent die.

14. The method of claim 13 , wherein the semiconductor wafer is singulated along the saw street between the two conductive vias to form full conductive vias.

15. The method of claim 9 , further including:

stacking the plurality of die to provide stacked die; and

electrically connecting the stacked die through the conductive vias.

16. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die;

forming a trench between the plurality of die to support the semiconductor wafer, the trench extending partially through the semiconductor wafer, a portion of the semiconductor wafer below the trench having sufficient thickness to maintain structural support for the semiconductor wafer during processing steps of:

(a) forming conductive vias between the plurality of die, and

(b) electrically connecting the conductive vias to contact pads on the plurality of die;

removing the portion of the semiconductor wafer below the trench along a backside of the semiconductor wafer; and

singulating the semiconductor wafer to separate the plurality of die.

17. The method of claim 16 , further including:

filling the trench with organic material;

forming a plurality of vias in the organic material;

forming traces between the contact pads and plurality of vias; and

depositing conductive material in the plurality of vias to form the conductive vias.

18. The method of claim 16 , wherein forming conductive vias includes forming one conductive via between the contact pads on adjacent die.

19. The method of claim 16 , wherein the semiconductor wafer is singulated through the conductive vias to form half conductive vias.

20. The method of claim 16 , wherein two conductive forming conductive vias includes forming two conductive vias side by side between the contact pads on adjacent die.

21. The method of claim 20 , wherein the semiconductor wafer is singulated along the saw street between the two conductive vias to form full conductive vias.

22. The method of claim 16 , further including:

stacking the plurality of die to provide stacked die; and

electrically connecting the stacked die through the conductive vias.