Semiconductor package having through-hole vias on saw streets formed with partial saw
View Patent ↗A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die. A trench is formed between the semiconductor die. The trench extending partially through the semiconductor wafer. The portion of the semiconductor wafer below the trench along a backside of the wafer maintaining structural support for the wafer during the processing steps of forming a plurality of conductive vias between the die, and forming traces to electrically connect the conductive vias to contact pads on the die. The portion of the semiconductor wafer below the trench along the backside of the wafer is removed. The semiconductor wafer is singulated to separate the die. The singulation can be performed through the conductive vias to make half conductive vias or between the conductive vias to make full conductive vias. The die can be stacked and electrically connected through the conductive vias.
1. A method of forming through-hole vias in a semiconductor wafer, comprising:
forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of the plurality of die, the semiconductor wafer having a saw street between the plurality of die;
forming a trench in the saw street, the trench extending partially through the semiconductor wafer, a portion of the semiconductor wafer below the trench along a backside of the semiconductor wafer maintaining structural support for the semiconductor wafer during processing steps of:
(a) filling the trench with organic material,
(b) forming a plurality of vias in the organic material,
(c) forming traces between the contact pads and plurality of vias, and
(d) depositing conductive material in the plurality of vias to form conductive vias;
removing the portion of the semiconductor wafer below the trench along the backside of the semiconductor wafer; and
singulating the semiconductor wafer along the saw street to separate the plurality of die.
2. The method of claim 1 , wherein to form conductive vias includes forming one conductive via between the contact pads on adjacent die.
3. The method of claim 1 , wherein the semiconductor wafer is singulated through the conductive vias to form half conductive vias electrically connected to the contact pads by the traces.
4. The method of claim 1 , wherein to form conductive vias includes forming two conductive vias side by side between the contact pads on adjacent die.
5. The method of claim 4 , wherein the semiconductor wafer is singulated along the saw street between the two conductive vias to form full conductive vias electrically connected to the contact pads by the traces.
6. The method of claim 1 , further including:
stacking the plurality of die to provide stacked die; and
electrically connecting the stacked die through the conductive vias.
7. A method of forming through-hole vias in a semiconductor wafer, comprising:
forming a semiconductor wafer having a plurality of die;
forming a trench between the plurality of die, the trench extending partially through the semiconductor wafer, a portion of the semiconductor wafer below the trench along a backside of the semiconductor wafer maintaining structural support for the semiconductor wafer during processing steps of:
(a) forming a plurality of conductive vias between the plurality of die, and
(b) forming traces to electrically connect the plurality of conductive vias to contact pads on the plurality of die;
removing the portion of the semiconductor wafer below the trench along the backside of the semiconductor wafer; and
singulating the semiconductor wafer to separate the plurality of die.
8. The method of claim 7 , further including:
filling the trench with organic material;
forming a plurality of vias in the organic material;
forming traces between the contact pads and plurality of vias; and
depositing conductive material in the plurality of vias to form the plurality of conductive vias.
9. The method of claim 7 , wherein forming a plurality of conductive vias includes forming one conductive via between the contact pads on adjacent die.
10. The method of claim 7 , wherein the semiconductor wafer is singulated through the plurality of conductive vias to form half conductive vias.
11. The method of claim 7 , wherein forming a plurality of conductive vias includes forming two conductive vias side by side between the contact pads on adjacent die.
12. The method of claim 11 , wherein the semiconductor wafer is singulated between the two conductive vias to form full conductive vias.
13. The method of claim 7 , further including:
stacking the plurality of die to provide stacked die; and
electrically connecting the stacked die through the plurality of conductive vias.
14. A method of forming through-hole vias in a semiconductor wafer, comprising:
forming a semiconductor wafer having a plurality of semiconductor die separated by a saw street;
forming a trench in the saw street between the plurality of semiconductor die, the trench extending partially through the semiconductor wafer, a portion of the semiconductor wafer remaining below the trench along a backside of the semiconductor wafer maintains structural support for the semiconductor wafer during processing steps of:
(a) forming a plurality of conductive vias in the saw street between the plurality of semiconductor die, and
(b) forming conductive traces to electrically connect the plurality of conductive vias to contact pads on the plurality of semiconductor die;
removing the portion of the semiconductor wafer below the trench along the backside of the semiconductor wafer; and
singulating the semiconductor wafer through the saw street to separate the plurality of semiconductor die.
15. The method of claim 14 , further including:
filling the trench with organic material;
forming a plurality of vias in the organic material;
forming conductive traces between the contact pads and plurality of vias; and
depositing conductive material in the plurality of vias to form the plurality of conductive vias.
16. The method of claim 14 , wherein forming a plurality of conductive vias includes forming one conductive via between the contact pads on adjacent semiconductor die.
17. The method of claim 14 , wherein the semiconductor wafer is singulated through the plurality of conductive vias to form half conductive vias.
18. The method of claim 14 , wherein forming a plurality of conductive vias includes forming two conductive vias side by side between the contact pads on adjacent semiconductor die.
19. The method of claim 18 , wherein the semiconductor wafer is singulated between the two conductive vias to form full conductive vias.
20. The method of claim 14 , further including:
stacking the plurality of semiconductor die to provide stacked semiconductor die; and
electrically connecting the stacked semiconductor die through the plurality of conductive vias.
21. The method of claim 14 , wherein the trench is centered between the plurality of semiconductor die.