Semiconductor package with controlled solder bump wetting
View Patent ↗A semiconductor package includes a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.
1. A semiconductor package, comprising:
a substrate having a plurality of lead fingers;
a plurality of stud bumps attached to the plurality of lead fingers, the plurality of stud bumps comprises a plurality of clusters of stud bumps, and the plurality of clusters of stud bumps comprise at least two stud bumps;
a die having a plurality solder bumps;
the plurality of solder bumps attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps; and
an encapsulant encapsulating the die, the electrical connections, and the lead fingers to expose a lower surface of the plurality of lead fingers.
2. The semiconductor package as claimed in claim 1 , wherein:
the plurality of solder bumps comprises a plurality of solder bumps having a first diameter; and
the plurality of stud bumps comprises a plurality of stud bumps having a second diameter smaller than or substantially equal to the first diameter.
3. The semiconductor package as claimed in claim 1 , wherein:
the plurality of stud bumps comprises stud bumps of at least one of copper, gold, and a combination thereof.
4. A semiconductor package, comprising:
a leadframe having a plurality of lead fingers;
a plurality of stud bumps, made from bond wire, attached to the plurality of lead fingers;
a die having a plurality solder bumps;
the plurality of solder bumps vertically aligned with and attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps, the plurality of stud bumps comprises a plurality of clusters of stud bumps, the plurality of clusters of stud bumps comprise at least two stud bumps; and
an encapsulant encapsulating the die, the electrical connections, and the lead fingers to expose a lower surface of the plurality of lead fingers.
5. The semiconductor package as claimed in claim 4 , wherein:
the plurality of solder bumps comprises a plurality of solder bumps having a first diameter; and
the plurality of stud bumps comprises a plurality of stud bumps having a second diameter smaller than or substantially equal to the first diameter.
6. The semiconductor package as claimed in claim 4 , wherein the plurality of stud bumps comprises stud bumps of at least one of copper, gold, and a combination thereof.