IP Library Granted Patent US 7,443,015
Granted Patent B2
US 7,443,015 · App. 11/381,734 · Granted Oct 28, 2008

Integrated circuit package system with downset lead

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 7,443,015
App. No.
11/381,734
Granted
Oct 28, 2008
Kind
B2
Abstract

An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.

Claims (24)

1. An integrated circuit package system comprising:

providing an integrated circuit package having a downset terminal lead;

forming a planar recessed lead surface, a terminal external surface, and a terminal top wall of the downset terminal lead, the planar recessed lead surface on a side opposite the terminal external surface, the terminal external surface substantially planar to a plane of a package bottom surface, and the terminal top wall adjacent the planar recessed lead surface, for controlling connector collapse;

attaching an integrated circuit over the planar recessed lead surface; and

forming a die paddle having a half-etched region for bump collapse control.

2. The system as claimed in claim 1 wherein forming the planar recessed lead surface comprises forming a half-etched region of the downset terminal lead.

3. The system as claimed in claim 1 further comprising forming a locking feature of the downset terminal lead for encapsulant integrity.

4. The system as claimed in claim 1 further comprising forming a die paddle having a mold locking feature for encapsulant integrity.

5. An integrated circuit package system comprising:

an integrated circuit package having a downset terminal lead;

a planar recessed lead surface, a terminal external surface, and a terminal top wall of the downset terminal lead, the planar recessed lead surface on a side opposite the terminal external surface, the terminal external surface substantially planar to a plane of a package bottom surface, and the terminal top wall adjacent the planar recessed lead surface, for controlling connector collapse;

an integrated circuit over the planar recessed lead surface; and a die paddle having a half-etched region for bump collapse control.

6. The system as claimed in claim 5 wherein the planar recessed lead surface comprises a half-etched region of the downset terminal lead.

7. The system as claimed in claim 5 further comprising a locking feature of the downset terminal lead for encapsulant integrity.

8. The system as claimed in claim 5 further comprising a die paddle having a mold locking feature for encapsulant integrity.

9. The system as claimed in claim 5 wherein:

the integrated circuit over the planar recessed lead surface of the downset terminal lead and the die paddle; and

the integrated circuit package having a die paddle and a downset terminal lead including a planar recessed lead surface, a terminal external surface, and a terminal top wall, the planar recessed lead surface on a side opposite the terminal external surface, the terminal external surface substantially coplanar to a plane of a package bottom surface, and the terminal top wall adjacent the planar recessed lead surface, for controlling connector collapse;

further comprising:

an electrical connector between the integrated circuit and the planar recessed lead surface.

10. The system as claimed in claim 9 wherein the integrated circuit package comprises a half-etched surface of the die paddle.

11. The system as claimed in claim 9 wherein the integrated circuit package comprises a partially half-etched surface of the die paddle.

12. The system as claimed in claim 9 wherein the integrated circuit package comprises the planar recessed lead surface at an inner edge of the downset terminal lead.

13. The system as claimed in claim 9 wherein the integrated circuit package comprises the planar recessed lead surface with a predetermined setback from an inner edge of the downset terminal leads.

Assignments (5)
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319) Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064760/0986 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052938/0305 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0319 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2006
From: PUNZALAN, JEFFREY D.; ALVAREZ, SHEILA MARIE L.; CAPARAS, JOSE ALVIN; QUIAZON, ROBINSON
To: STATS CHIPPAC LTD.
Reel/Frame 017576/0126 →
Continuity (2)
Provisional Application 6059477600 · May 5, 2005
Related Publication 20070108624A1 · May 17, 2007