Waferscale package system

1. A waferscale package system comprising:

forming a protection structure comprises:

forming a wafer,

fabricating a device element on the wafer,

forming a waferscale spacer around the device element and having a thickness greater than a width thereof and greater than the thickness of the device element, and

attaching a waferscale cap to the waferscale spacer to cover the device element;

attaching a carrier to the protection structure;

electrically connecting the wafer outside the waferscale spacer to the carrier with bond wires; and

molding an encapsulant around the protection structure to the carrier.

2. The system as claimed in claim 1 wherein fabricating the device element on the wafer comprises fabricating a microelectromechanical system element.

3. The system as claimed in claim 1 wherein fabricating the device element on the wafer comprises fabricating an optical element with the waferscale cap optically transparent.

4. The system as claimed in claim 1 wherein forming the waferscale spacer around the device element comprises forming a dam type waferscale spacer with the waferscale cap for preventing the encapsulant from interfering with the device element.

5. The system as claimed in claim 1 wherein forming the waferscale spacer around the device element comprises forming a step-dam type waferscale spacer with the waferscale cap, on a step of the step-dam waferscale spacer, for preventing the encapsulant from interfering with the device element.

6. A waferscale package system comprising:

forming a protection structure comprises:

forming a wafer,

fabricating a device element on the wafer,

forming a waferscale spacer around the device element and having a thickness greater than width thereof and greater than the thickness of the device element,

attaching a waferscale cap to the waferscale spacer to cover the device element, and singulating the wafer to form a number of a semiconductor die;

attaching a carrier to the protection structure;

electrically connecting the semiconductor die outside the waferscale spacer to the carrier with bond wires; and

molding an encapsulant around the protection structure to the carrier.

7. The system as claimed in claim 6 wherein molding the encapsulant around the protection structure to the carrier comprises exposing a top of the waferscale cap.

8. The system as claimed in claim 6 wherein molding the encapsulant around the protection structure to the carrier comprises forming a hermetic seal of the protection structure.

9. The system as claimed in claim 6 wherein forming the wafer comprises forming an optical structure.

10. The system as claimed in claim 6 further comprising attaching electrical interconnects between carrier and bonding pads of the semiconductor die.

11. A waferscale package system comprising:

a protection structure comprises:

a semiconductor die,

a device element on the semiconductor die,

a waferscale spacer around the device element and having a thickness greater than a width thereof and greater than the thickness of the device element, and

a waferscale cap attached to the waferscale spacer to cover the device element;

a carrier attached to the protection structure;

bond wires electrically connecting the wafer outside the waferscale spacer to the carrier; and

an encapsulant around the protection structure to the carrier.

12. The system as claimed in claim 11 wherein the device element on the semiconductor die is a microelectromechanical system element.

13. The system as claimed in claim 11 wherein the device element on the semiconductor die is an optical element with the waferscale cap optically transparent.

14. The system as claimed in claim 11 wherein the waferscale spacer around the device element is a dam type waferscale spacer with the waferscale cap for preventing the encapsulant from interfering with the device element.

15. The system as claimed in claim 11 wherein the waferscale spacer around the device element is a step-dam type waferscale spacer with the waferscale cap, on a step of the step-dam waferscale spacer, for preventing the encapsulant from interfering with the device element.

16. The system as claimed in claim 11 wherein the carrier is a substrate or lead frame.

17. The system as claimed in claim 16 wherein the encapsulant around the protection structure to the carrier comprises a top of the waferscale cap exposed.

18. The system as claimed in claim 16 wherein the encapsulant around the protection structure to the carrier forms a hermetic seal by the encapsulant of the protection structure.

19. The system as claimed in claim 16 wherein the semiconductor die supports an optical structure.

20. The system as claimed in claim 16 further comprising electrical interconnects between carrier and bonding pads of the semiconductor die.