Integrated circuit packaging system with patterned substrate and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having a component side and a system side;

depositing a solder resist layer on the component side of the package substrate, the solder resist layer having a thickness range of 50 to 150 μm for preventing warpage of the package substrate;

patterning groups of access openings and a die mount opening in the solder resist layer;

attaching an integrated circuit die in the die mount opening;

forming conductive contacts in the access openings; and

attaching system interconnects to the system side of the package substrate.

2. The method as claimed in claim 1 further comprising forming component contacts on the component side coupled to system contacts on the system side through internal circuitry.

3. The method as claimed in claim 1 further comprising establishing a separation distance between the access openings in the groups.

4. The method as claimed in claim 1 wherein forming the conductive contacts includes forming elevated contacts in the access openings.

5. The method as claimed in claim 1 further comprising attaching a second integrated circuit packaging system to the conductive contacts by coupling system interconnects of the second integrated circuit packaging system to the conductive contacts.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having a component side and a system side includes component contacts on the component side coupled to system contacts on the system side through traces and vias;

depositing a solder resist layer on the component side of the package substrate includes applying a dry photoresist or liquid photoresist on the component side, the solder resist layer having a thickness range of 50 to 150 μm for preventing warpage of the package substrate;

patterning groups of access openings and a die mount opening in the solder resist layer;

attaching an integrated circuit die in the die mount opening includes coupling chip interconnects between the component contacts and the integrated circuit die;

forming conductive contacts in the access openings includes forming elevated contacts; and

attaching system interconnects to the system side of the package substrate.

7. The method as claimed in claim 6 wherein depositing the solder resist layer on the component side includes the solder resist layer having the thickness in the range of 50 to 100 μm measured from the component side.

8. The method as claimed in claim 6 further comprising establishing a separation distance between the access openings in the groups including allowing the elevated contacts to encroach the separation distance without coupling to the elevated contact in an adjacent position.

9. The method as claimed in claim 6 further comprising applying a liquid adhesive between the integrated circuit die and the component side, the liquid adhesive bordered by the die mount opening.

10. The method as claimed in claim 6 further comprising attaching a second integrated circuit packaging system to the conductive contacts by coupling system interconnects of the second integrated circuit packaging system to the conductive contacts, the second integrated circuit packaging system includes a second integrated circuit die; and the integrated circuit die, the conductive contacts of the integrated circuit packaging system, or a combination thereof electrically connected to the second integrated circuit packaging system.

11. An integrated circuit packaging system comprising:

a package substrate having a component side and a system side;

a solder resist layer, on the component side of the package substrate, having groups of access openings and a die mount opening patterned therein, the solder resist layer having a thickness range of 50 to 150 μm for preventing warpage of the package substrate;

an integrated circuit die attached in the die mount opening;

conductive contacts formed in the access openings; and

system interconnects attached to the system side of the package substrate.

12. The system as claimed in claim 11 further comprising component contacts on the component side coupled to system contacts on the system side by internal circuitry.

13. The system as claimed in claim 11 wherein the groups of the access openings include a first of the access openings patterned a separation distance away from a second of the access openings.

14. The system as claimed in claim 11 wherein the conductive contacts in the access openings are elevated contacts.

15. The system as claimed in claim 11 further comprising a second integrated circuit packaging system coupled to the conductive contacts by system interconnects of the second integrated circuit packaging system.

16. The system as claimed in claim 11 wherein:

the solder resist layer includes a dry photoresist or liquid photoresist on the component side;

the conductive contacts are elevated contacts; and

component contacts on the component side coupled to system contacts on the system side through traces and vias.

17. The system as claimed in claim 16 wherein the solder resist layer on the component side includes the thickness of the solder resist layer in the range of 50 to 150 μm measured from the component side.

18. The system as claimed in claim 16 wherein the groups of the access openings include a first of the access openings patterned a separation distance away from a second of the access openings in which the elevated contacts encroach the separation distance but do not couple to the elevated contacts in an adjacent position.

19. The system as claimed in claim 16 further comprising a liquid adhesive between the integrated circuit die and the component side, the liquid adhesive bordered by the die mount opening.

20. The system as claimed in claim 16 further comprising a second integrated circuit packaging system attached to the conductive contacts by system interconnects of the second integrated circuit packaging system, the second integrated circuit packaging system includes a second integrated circuit die; and

wherein the integrated circuit die, the conductive contacts of the integrated circuit packaging system, or a combination thereof are electrically connected to the second integrated circuit packaging system.