Patent Assignment
Reel/Frame 039514/0451
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
Recorded: 2016-07-26
Received: 2016-07-26
Pages: 11
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, 569059, SINGAPORE
Covered Applications
(42)
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
App. No. 14/341,578
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/211,303
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
App. No. 13/209,837
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP BONDED DIES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/039,309
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/038,384
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/819,162
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/777,615
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PATTERNED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/714,291
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/563,368
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/542,097
→
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH REDISTRIBUTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/483,548
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF
App. No. 12/412,886
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/408,641
→
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
App. No. 12/260,089
→
RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM
App. No. 12/182,132
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/122,639
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/056,402
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION
App. No. 12/055,612
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE
App. No. 11/857,188
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE
App. No. 11/767,820
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE
App. No. 11/749,712
→
SEMICONDUCTOR PACKAGE WIRE BONDING
App. No. 11/672,910
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/532,508
→
BUMP FOR OVERHANG DEVICE
App. No. 11/469,307
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 11/458,065
→
Epoxy Bump for Overhang Die
App. No. 11/420,853
→
SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM
App. No. 11/383,802
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/380,587
→
MULTICHIP PACKAGE SYSTEM
App. No. 11/379,018
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/279,741
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
App. No. 11/278,002
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/276,947
→
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM
App. No. 11/307,498
→
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING DIE-ATTACH PAD WITH ELEVATED BONDLINE THICKNESS
App. No. 11/307,349
→
INTEGRATED CIRCUIT SYSTEM WITH WAFERSCALE SPACER SYSTEM
App. No. 11/307,317
→
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
App. No. 11/163,547
→
STACKED DIE PACKAGING SYSTEM
App. No. 11/163,313
→
SUBSTRATE INDEXING SYSTEM
App. No. 11/162,971
→
HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
App. No. 11/162,828
→
INTEGRATED CIRCUIT PACKAGE WITH DIFFERENT HARDNESS BUMP PAD AND BUMP AND MANUFACTURING METHOD THEREFOR
App. No. 10/908,254
→
Under bump metallurgy in integrated circuits
App. No. 11/035,637
→
Wire sweep resistant semiconductor package and manufacturing method thereof
App. No. 10/934,835
→