IP Library Patent Application 11383802
Patent Application
App. No. 11/383,802

SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM

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Quick Facts
Patent No.
US None
App. No.
11/383,802
Abstract

A spacerless semiconductor package chip stacking system is provided having a substrate. The substrate has at least one window therethrough. A first semiconductor device is attached face down on the top of the substrate. A second semiconductor device is attached face up on the back of the first semiconductor device. The first semiconductor device is electrically connected through the window to the bottom of the substrate. The second semiconductor device is electrically connected to the substrate.

Claims (49)

1 . A spacerless semiconductor package chip stacking system, comprising:

providing a substrate having at least one window therethrough;

attaching a first semiconductor device face down on the top of the substrate;

attaching a second semiconductor device face up on the back of the first semiconductor device;

electrically connecting the first semiconductor device through the window to the bottom of the substrate; and

electrically connecting the second semiconductor device to the substrate.

2 . The system as claimed in claim 1 further comprising attaching the first and second semiconductor devices to one another prior to attaching the first semiconductor device to the substrate.

3 . The system as claimed in claim 1 further comprising providing external electrical connections for the substrate on the bottom side thereof opposite the semiconductor devices.

4 . The system as claimed in claim 1 in which the first and second semiconductor devices are substantially the same size.

5 . The system as claimed in claim 1 :

in which attaching a second semiconductor device face up on the back of the first semiconductor device further comprises attaching the semiconductor devices to one another with an adhesive;

in which attaching a first semiconductor device face down on the top of the substrate further comprises attaching the first semiconductor device to the substrate with an adhesive; and

further comprising curing the adhesives simultaneously.

6 . A spacerless semiconductor package chip stacking system, comprising:

providing a substrate having at least one window therethrough;

attaching a first semiconductor device face down with a film adhesive or a pre-applied adhesive on the top of the substrate;

attaching a second semiconductor device face up with a film adhesive or a pre-applied adhesive on the back of the first semiconductor device;

electrically connecting the first semiconductor device through the window to the bottom of the substrate;

electrically connecting the second semiconductor device to the substrate;

sealing and encapsulating the window in a lower encapsulation portion; and

encapsulating the semiconductor devices and at least a portion of the substrate.

7 . The system as claimed in claim 6 further comprising attaching the first and second semiconductor devices to one another prior to attaching the first semiconductor device to the substrate.

8 . The system as claimed in claim 6 further comprising providing external ball grid array or pin grid array electrical connections for the substrate on the bottom side thereof opposite the semiconductor devices.

9 . The system as claimed in claim 6 in which the first and second semiconductor devices are the same size.

10 . The system as claimed in claim 6 further comprising curing the adhesives simultaneously.

11 . A spacerless semiconductor package chip stacking system, comprising:

a substrate having at least one window therethrough;

a first semiconductor device attached face down on the top of the substrate;

a second semiconductor device attached face up on the back of the first semiconductor device;

conductors electrically connecting the first semiconductor device through the window to the bottom of the substrate; and

conductors electrically connecting the second semiconductor device to the substrate.

12 . The system as claimed in claim 11 in which the first and second semiconductor devices are substantially the same size.

13 . The system as claimed in claim 11 in which the first and second semiconductor devices are of different sizes.

14 . The system as claimed in claim 11 further comprising external electrical connections for the substrate on the bottom side thereof opposite the semiconductor devices.

15 . The system as claimed in claim 11 further comprising:

an adhesive attaching the semiconductor devices to one another;

an adhesive attaching the first semiconductor device to the substrate; and

the adhesives having the characteristics of having been cured simultaneously.

16 . The system as claimed in claim 11 :

in which the conductors are bonding wires; and

further comprising:

a film adhesive or a pre-applied adhesive attaching the first semiconductor device on the substrate;

a film adhesive or a pre-applied adhesive attaching the second semiconductor device on the first semiconductor device;

a lower encapsulation portion sealing and encapsulating the window; and

an encapsulant encapsulating the semiconductor devices and at least a portion of the substrate.

17 . The system as claimed in claim 16 in which the first and second semiconductor devices are the same size.

18 . The system as claimed in claim 16 in which the first and second semiconductor devices are of different sizes.

19 . The system as claimed in claim 16 further comprising external ball grid array or pin grid array electrical connections for the substrate on the bottom side thereof opposite the semiconductor devices.

20 . The system as claimed in claim 16 in which the adhesives further comprise adhesives that have the characteristics of having been cured simultaneously.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039980/0838 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 039514/0451 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0442 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2006
From: AHN, SEUNGYUN; KIM, YOUNGCHEOL; CHOI, HAENGCHEOL; LEE, MYUNG KIL; BAE, JOHYUN; BAE, HYUNIL; MYUNG, JUNWOO
To: STATS CHIPPAC LTD.
Reel/Frame 017631/0416 →