IP Library Patent Application 12563368
Patent Application
App. No. 12/563,368

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF

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Quick Facts
Patent No.
US None
App. No.
12/563,368
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a shielding channel through a substrate first side and a substrate second side; mounting a first shielding interconnect to the shielding channel; mounting an integrated circuit over the substrate and adjacent to the first shielding interconnect; attaching a silicon interposer, having an integral-conductive-shield and a via, to the first shielding interconnect with the integral-conductive-shield over the integrated circuit; grounding the shielding channel at the substrate second side; and forming an encapsulation over the substrate covering the integrated circuit and the first shielding interconnect.

Claims (56)

1 . A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate having a shielding channel through a substrate first side and a substrate second side;

mounting a first shielding interconnect to the shielding channel;

mounting an integrated circuit over the substrate and adjacent to the first shielding interconnect;

attaching a silicon interposer, having an integral-conductive-shield and a via, to the first shielding interconnect with the integral-conductive-shield over the integrated circuit;

grounding the shielding channel at the substrate second side; and

forming an encapsulation over the substrate covering the integrated circuit and the first shielding interconnect.

2 . The method as claimed in claim 1 wherein forming the encapsulation includes forming the encapsulation planar with a silicon interposer first side that is exposed from the encapsulation.

3 . The method as claimed in claim 1 wherein the attaching the silicon interposer includes attaching the integral-conductive-shield to the first shielding interconnect.

4 . The method as claimed in claim 1 further comprising:

attaching an embedded interconnect to the silicon interposer; and

wherein forming the encapsulation includes forming the encapsulation around and exposing the embedded interconnect.

5 . The method as claimed in claim 1 further comprising mounting an internal device over the substrate between the integrated circuit and the first shielding interconnect.

6 . A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate having a shielding channel through a substrate first side and a substrate second side;

mounting a first shielding interconnect to the shielding channel;

mounting an integrated circuit over the substrate and facing the substrate first side with the integrated circuit adjacent to the first shielding interconnect;

mounting an internal interconnect over the substrate first side;

attaching a silicon interposer, having an integral-conductive-shield, a contact pad, and a via, to the first shielding interconnect and the internal interconnect with the integral-conductive-shield over the integrated circuit;

mounting a second shielding interconnect to the shielding channel along the substrate second side;

grounding the second shielding interconnect at the substrate second side; and

forming an encapsulation over the substrate covering the integrated circuit and the first shielding interconnect.

7 . The method as claimed in claim 6 further comprising:

mounting an integrated circuit die stack over the silicon interposer; and

wherein forming the encapsulation includes forming the encapsulation over the integrated circuit die stack.

8 . The method as claimed in claim 6 further comprising:

mounting an integrated circuit device over the silicon interposer; and

wherein forming the encapsulation includes forming the encapsulation over the integrated circuit device.

9 . The method as claimed in claim 6 wherein mounting the second shielding interconnect includes attaching an external interconnect to the substrate second side.

10 . The method as claimed in claim 6 wherein mounting the integrated circuit over the substrate includes mounting a flip-chip.

11 . An integrated circuit packaging system comprising:

a substrate having a shielding channel through a substrate first side and a substrate second side with the shielding channel grounded at the substrate second side;

a first shielding interconnect mounted to the shielding channel;

an integrated circuit mounted over the substrate and adjacent to the first shielding interconnect;

a silicon interposer, having an integral-conductive-shield and a via, attached to the first shielding interconnect with the integral-conductive-shield over the integrated circuit; and

an encapsulation over the substrate covering the integrated circuit and the first shielding interconnect.

12 . The system as claimed in claim 11 wherein the encapsulation is planar with a silicon interposer first side that is exposed from the encapsulation.

13 . The system as claimed in claim 11 wherein the silicon interposer includes the integral-conductive-shield attached to the first shielding interconnect.

14 . The system as claimed in claim 11 further comprising:

an embedded interconnect attached to the silicon interposer; and

wherein the encapsulation is around and exposes the embedded interconnect.

15 . The system as claimed in claim 11 further comprising an internal device mounted over the substrate between the integrated circuit and the first shielding interconnect.

16 . The system as claimed in claim 11 further comprising:

a contact pad exposed at a silicon interposer first side;

an internal interconnect mounted over the substrate first side; and

wherein:

the silicon interposer is attached to the internal interconnect; and

the integral-conductive-shield is along a silicon interposer second side.

17 . The system as claimed in claim 16 further comprising:

an integrated circuit die stack mounted over the silicon interposer; and

wherein the encapsulation is over the integrated circuit die stack.

18 . The system as claimed in claim 16 further comprising:

an integrated circuit device mounted over the silicon interposer; and

wherein the encapsulation is over the integrated circuit device.

19 . The system as claimed in claim 16 further comprising an external interconnect attached to the substrate second side.

20 . The system as claimed in claim 16 wherein the integrated circuit mounted over the substrate includes a flip-chip.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039980/0838 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 039514/0451 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0442 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2009
From: CHO, NAMJU; CHI, HEEJO; SHIN, HANGIL
To: STATS CHIPPAC LTD.
Reel/Frame 023309/0275 →