INTEGRATED CIRCUIT SYSTEM WITH WAFERSCALE SPACER SYSTEM
An integrated circuit system is provided including forming integrated circuits on a wafer using a semiconductor manufacturing process; forming a waferscale spacer system on the integrated circuits on the wafer using the semiconductor manufacturing process; and singulating the wafer to have portions of the waferscale spacer system on the integrated circuits after singulation.
1 . An integrated circuit system comprising: forming integrated circuits on a wafer using a semiconductor manufacturing process; forming a waferscale spacer system on the integrated circuits on the wafer using the semiconductor manufacturing process; and singulating the wafer to have portions of the waferscale spacer system on the integrated circuits after singulation.
2 . The system as claimed in claim 1 wherein forming the waferscale spacer system includes forming a spacer with a geometric configuration.
3 . The system as claimed in claim 1 wherein forming the waferscale spacer system includes forming a spacer within another spacer.
4 . The system as claimed in claim 1 wherein forming the waferscale spacer system includes forming spacers having the same configuration on different integrated circuits on the wafer.
5 . The system as claimed in claim 1 wherein forming the waferscale spacer system includes forming spacers having different configurations on different integrated circuits on the wafer.
6 . An integrated circuit system comprising:
forming integrated circuits on a wafer using a semiconductor manufacturing removal process;
depositing a spacer material on an active side of the integrated circuits on the wafer;
forming a waferscale spacer system on the integrated circuits on the wafer by selectively removing portions of the spacer material using the semiconductor manufacturing removal process; and
singulating the wafer to have portions of the waferscale spacer system on the integrated circuits after singulation.
7 . The system as claimed in claim 6 wherein forming the waferscale spacer system includes forming a spacer with a geometric configuration comprised of a dot, block, geometric shape, straight line, angled line, or a combination thereof.
8 . The system as claimed in claim 6 wherein forming the waferscale spacer system includes forming a plurality of spacers within another spacer.
9 . The system as claimed in claim 6 wherein:
forming the waferscale spacer system includes forming spacers having the same configuration on different integrated circuits on the wafer; and
stacking an additional integrated circuit on at least one of the different integrated circuits.
10 . The system as claimed in claim 6 wherein:
forming the waferscale spacer system includes forming spacers having different configurations on different integrated circuits on the wafer; and
stacking an additional integrated circuit on at least one of the different integrated circuits.
11 . An integrated circuit system comprising:
a substrate;
an integrated circuit attached to the substrate; and
a waferscale spacer system on the integrated circuit.
12 . The system as claimed in claim 11 wherein the waferscale spacer system includes a spacer with a geometric configuration.
13 . The system as claimed in claim 11 wherein the waferscale spacer system includes a spacer within another spacer.
14 . The system as claimed in claim 11 further comprising:
an additional integrated circuit stacked on the waferscale spacer system; and
an encapsulant encapsulating the integrated circuit, the additional integrated circuit, and the waferscale spacer system.
15 . The system as claimed in claim 11 further comprising: bond wires connecting the integrated circuit to the substrate; and external interconnects on the substrate operatively connected to the bond wires.
16 . The system as claimed in claim 11 further comprising:
an additional integrated circuit stacked on the waferscale spacer system, the additional integrated circuit of a different size from the integrated circuit, the additional integrated circuit having an additional waferscale spacer system thereon;
a further integrated circuit stacked on the additional waferscale spacer system, the further integrated circuit of a different size from the integrated circuit and the additional integrated circuit; and
an encapsulant encapsulating the integrated circuit, the waferscale spacer system the additional integrated circuit, the additional waferscale spacer system, and the further integrated circuit.
17 . The system as claimed in claim 16 wherein the waferscale spacer system includes forming a spacer with a geometric configuration comprised of a dot, block, geometric shape, straight line, angled line, or a combination thereof.
18 . The system as claimed in claim 16 wherein the waferscale spacer system includes forming a plurality of spacers within another spacer.
19 . The system as claimed in claim 16 further comprising:
an additional integrated circuit stacked on the waferscale spacer system;
bond wires for connecting the integrated circuit and the additional integrated circuit to the substrate; and
an encapsulant encapsulating the integrated circuit, the additional integrated circuit, and the waferscale spacer system.
20 . The system as claimed in claim 16 further comprising:
an additional integrated circuit stacked on the waferscale spacer system, the additional integrated circuit of a different size from the integrated circuit, the additional integrated circuit having an additional waferscale spacer system thereon;
a further integrated circuit stacked on the additional waferscale spacer system, the further integrated circuit of a different size from the integrated circuit and the additional integrated circuit;
bond wires for connecting the integrated circuit, the additional integrated circuit, and the further integrated circuit to the substrate; and
an encapsulant encapsulating the integrated circuit, the waferscale spacer system the additional integrated circuit, the additional waferscale spacer system, and the further integrated circuit.