Integrated circuit package system with multi-chip module

1. A method for manufacturing an integrated circuit package system with multi-chip module comprising:

providing an upper substrate having an upper chip thereon;

positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon;

encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed from the chip encapsulant;

mounting the lower chip over the lower substrate with the bottom interconnects extended through a gap between the chip encapsulant and the lower substrate, the bottom interconnects directly on the lower substrate, the chip encapsulant fully separated from the lower substrate by the gap; and

filling the gap with a package encapsulant with a portion of a surface of the upper substrate opposite the upper chip covered by the package encapsulant.

2. The method as claimed in claim 1 further comprising interconnecting the upper chip and the upper substrate.

3. The method as claimed in claim 1 further comprising spacing the upper chip from the lower chip to prevent contact between interconnections between the upper chip and the upper substrate, and the lower chip.

4. The method as claimed in claim 1 wherein positioning the lower chip positions a lower chip larger than the upper chip.

5. The method as claimed in claim 1 further comprising:

providing a middle substrate having a middle chip thereon;

connecting the upper chip to the middle substrate; and

connecting the middle substrate to the lower substrate.

6. The method as claimed in claim 1 wherein:

providing the upper substrate provides the upper substrate with an opening provided therein; and

interconnecting the upper chip and the upper substrate through the opening.

7. The method as claimed in claim 1 further comprising connecting a second package to the upper substrate.

8. A method for manufacturing an integrated circuit package system with multi-chip module comprising:

providing an upper substrate having an upper chip thereon and having interconnects therebetween;

positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon;

encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed from the chip encapsulant;

mounting the lower chip over the lower substrate with the bottom interconnects extended through a gap between the chip encapsulant and the lower substrate, the bottom interconnects directly on the lower substrate, the chip encapsulant fully separated from the lower substrate by the gap;

interconnecting the upper substrate and the lower substrate; and

filling the gap with a package encapsulant with a portion of a surface of the upper substrate opposite the upper chip covered by the package encapsulant.

9. The method as claimed in claim 8 further comprising interconnecting the upper chip and the upper substrate by solder bumps or bond wires.

10. The method as claimed in claim 8 further comprising spacing the upper chip from the lower chip to prevent contact between interconnections between the upper chip and the upper substrate, and the lower chip wherein the interconnections are bond wires.

11. The method as claimed in claim 8 wherein positioning the lower chip positions a lower chip larger than the upper chip and having a spacer therebetween.

12. The method as claimed in claim 8 further comprising:

providing a middle substrate having a middle chip thereon and having interconnects therebetween;

connecting the upper chip to the middle substrate by interconnects therebetween; and

connecting the middle substrate to the lower substrate by a stud or solder ball in the chip encapsulant.

13. The method as claimed in claim 8 wherein:

providing the upper substrate provides the upper substrate with an opening provided therein; and

interconnecting the upper chip and the upper substrate through the opening using bond wires.

14. The method as claimed in claim 8 wherein:

filling the gap with package encapsulant leaves the upper substrate exposed; and

connecting a known-good package to the exposed upper substrate.