INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
An integrated circuit package system is provided providing an integrated circuit die having a final metal layer of the semiconductor process used to manufacture the integrated circuit die and a passivation layer provided thereon, depositing a first metal layer on the passivation layer and the final metal layer, forming an analog circuit in the first metal layer, coating a first insulation layer on the first metal layer and the passivation layer, exposing a first pad and a second pad of the first metal layer through the first insulation layer, and connecting a first interconnect on the first pad and a second interconnect on the second pad.
1 . An integrated circuit package system comprising:
providing an integrated circuit die having a final metal layer of the semiconductor process used to manufacture the integrated circuit die and a passivation layer provided thereon;
depositing a first metal layer on the passivation layer and the final metal layer;
forming an analog circuit with the final metal layer;
coating a first insulation layer on the first metal layer and the passivation layer;
exposing a first pad and a second pad of the first metal layer through the first insulation layer; and
connecting a first interconnect on the first pad and a second interconnect on the second pad.
2 . The system as claimed in claim 1 further comprising forming a bridge with the final metal layer for the analog circuit.
3 . The system as claimed in claim 1 further comprising forming a bridge with the first metal layer for the analog circuit.
4 . The system as claimed in claim 1 further comprising forming an under bump metallization on the first pad.
5 . The system as claimed in claim 1 wherein depositing the first metal layer comprises forming a stack of layers of different metals or alloys.
6 . An integrated circuit package system comprising:
providing an integrated circuit die having a final metal layer of the semiconductor process used to manufacture the integrated circuit die and a passivation layer provided thereon;
forming an analog circuit with the final metal layer:
depositing a first metal layer on the passivation layer and the final metal layer;
coating a first insulation layer on the first metal layer and the passivation layer;
depositing a second metal layer on the first insulation layer and the first metal layer;
coating a second insulation layer on the second metal layer;
exposing a protective pad of the first metal layer;
exposing a bump pad of the second metal layer through the second insulation layer; and
connecting a bond wire on the protective pad and a solder ball on the bump pad.
7 . The system as claimed in claim 6 wherein forming the analog circuit comprises forming a passive analog circuit element.
8 . The system as claimed in claim 6 further comprising forming a bridge with the first metal layer for the analog circuit.
9 . The system as claimed in claim 6 further comprising forming a bridge with the first metal layer for the second metal layer.
10 . The system as claimed in claim 6 wherein depositing the second metal layer comprises forming a stack of layers of different metals or alloys.
11 . An integrated circuit package system comprising:
an integrated circuit die having a final metal layer of the semiconductor process used to manufacture the integrated circuit die and a passivation layer provided thereon;
a first metal layer on the passivation layer and the final metal layer;
an analog circuit with the final metal layer;
a first insulation layer on the first metal layer and the passivation layer;
a first pad and a second pad of the first metal layer exposed through the first insulation layer; and
a first interconnect on the first pad and a second interconnect on the second pad.
12 . The system as claimed in claim 11 further comprising a bridge with the final metal layer for the analog circuit.
13 . The system as claimed in claim 11 further comprising a bridge with the first metal layer for the analog circuit.
14 . The system as claimed in claim 11 further comprising an under bump metallization on the first pad.
15 . The system as claimed in claim 11 wherein the first metal layer includes a stack of layers of different metals or alloys.
16 . The system as claimed in claim 11 wherein:
the integrated circuit die having the final metal layer of the semiconductor process used to manufacture the integrated circuit die and the passivation layer provided thereon has an active side;
the first metal layer on the passivation layer and the final metal layer is a redistribution layer;
the first insulation layer on the first metal layer and the passivation layer is made of a polymer;
the first pad of the first metal layer exposed is a protective pad; and
the first interconnect on the first pad is a bond wire; and further comprising:
a second metal layer on the first insulation layer and the first metal layer;
a second insulation layer on the second metal layer;
the analog circuit in the second metal layer;
exposing a bump pad of the second metal layer through the second insulation layer; and
a solder ball on the bump pad.
17 . The system as claimed in claim 16 wherein the analog circuit is a passive analog circuit element.
18 . The system as claimed in claim 16 further comprising a bridge with the first metal layer for the analog circuit.
19 . The system as claimed in claim 16 further comprising a bridge with the first metal layer for the second metal layer.
20 . The system as claimed in claim 16 wherein the second metal layer comprises a stack of layers of different metals or alloys.