Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process
A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.
1 . A semiconductor device, comprising:
a substrate having a plurality of semiconductor devices formed on a surface of the substrate;
a contact pad formed over the substrate in electrical contact with the semiconductor devices;
a redistribution layer (RDL) formed over the substrate in electrical contact with the contact pad;
a passivation layer formed over the substrate and RDL, wherein a portion of the passivation layer is removed to expose the RDL;
an adhesive layer formed over the passivation layer and the exposed RDL;
a barrier layer formed over a first portion of the adhesive layer which is over the exposed RDL, the barrier layer not being formed over a second portion of the adhesive layer;
a wetting layer formed over the barrier layer which is over the first portion of the adhesive layer, the wetting layer not being formed over the second portion of the adhesive layer; and
a bump formed over the wetting layer and barrier layer.
2 . The semiconductor device of claim 1 , wherein the first portion of the adhesive layer is removed after the bump is formed.
3 . The semiconductor device of claim 1 , wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
4 . The semiconductor device of claim 1 , wherein the adhesive layer follows a contour of the passivation layer.
5 . A semiconductor device, comprising:
a substrate;
a passivation layer formed over the substrate;
an adhesive layer formed over the passivation layer;
a barrier layer formed over a first portion of the adhesive layer, the barrier layer not being formed over a second portion of the adhesive layer;
a wetting layer formed over the barrier layer over the first portion of the adhesive layer, the wetting layer not being formed over the second portion of the adhesive layer; and
an electrical interconnect formed over the wetting layer and barrier layer.
6 . The semiconductor device of claim 5 , further including a plurality of semiconductor devices formed on a surface of the substrate.
7 . The semiconductor device of claim 5 , further including:
a contact pad formed over the substrate; and
a redistribution layer (RDL) formed over the substrate in electrical contact with the contact pad.
8 . The semiconductor device of claim 7 , wherein the passivation layer is formed over the RDL and a portion of the passivation layer is removed to expose the RDL.
9 . The semiconductor device of claim 8 , wherein the barrier layer is formed over the first portion of the adhesive layer which is over the exposed RDL.
10 . The semiconductor device of claim 5 , wherein the first portion of adhesive layer is removed after the bump is formed.
11 . The semiconductor device of claim 5 , wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
12 . The semiconductor device of claim 5 , wherein the adhesive layer follows a contour of the passivation layer.
13 . The semiconductor device of claim 5 , wherein the electrical interconnect includes a bump.
14 . A semiconductor device, comprising:
a substrate;
a passivation layer formed over the substrate;
an adhesive layer formed over the passivation layer;
a wetting layer formed over a first portion of the adhesive layer, the wetting layer not being formed over a second portion of the adhesive layer; and
an electrical interconnect formed over the wetting layer.
15 . The semiconductor device of claim 14 , further including a barrier layer formed between the adhesive layer and the wetting layer.
16 . The semiconductor device of claim 15 , wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
17 . The semiconductor device of claim 14 , further including:
a contact pad formed over the substrate; and
a redistribution layer formed over the substrate in electrical contact with the contact pad.
18 . The semiconductor device of claim 14 , wherein the first portion of adhesive layer is removed after the bump is formed.
19 . The semiconductor device of claim 14 , wherein the electrical interconnect includes a bump.
20 . A semiconductor device, comprising:
a substrate;
a passivation layer formed over the substrate;
an adhesive layer formed over the passivation layer;
a barrier layer formed over a first portion of the adhesive layer, the barrier layer not being formed over a second portion of the adhesive layer; and
an electrical interconnect formed over the barrier layer.
21 . The semiconductor device of claim 20 , further including a wetting layer formed over the barrier layer which is over the first portion of the adhesive layer, the wetting layer not being formed over the second portion of the adhesive layer.
22 . The semiconductor device of claim 21 , wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
23 . The semiconductor device of claim 20 , further including:
a contact pad formed over the substrate; and
a redistribution layer formed over the substrate in electrical contact with the contact pad.
24 . The semiconductor device of claim 20 , wherein the first portion of adhesive layer is removed after the bump is formed.
25 . The semiconductor device of claim 20 , wherein the electrical interconnect includes a bump.