IP Library Granted Patent US 9,123,663
Granted Patent B2
US 9,123,663 · App. 12/136,682 · Granted Sep 1, 2015

Semiconductor device and method of forming shielding layer grounded through metal pillars formed in peripheral region of the semiconductor

Inventors: OhHan Kim (Kyunggi-Do, KR); SeungWon Kim (Kyunggi-Do, KR); JoungUn Park (Kyunggi-do, KR)
Assignee: STATS ChipPAC, Ltd.
H01L23/3121H01L21/561H01L23/29H01L23/3128H01L23/552H01L24/97H01L24/48H01L2224/16225H01L2224/48091H01L2224/97H01L2924/0103H01L2924/01004H01L2924/01006H01L2924/01013H01L2924/01029H01L2924/01047H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/01322H01L2924/09701H01L2924/14H01L2924/1433H01L2924/15311H01L2924/19041H01L2924/3011H01L2924/3025H01L2924/30105
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Quick Facts
Patent No.
US 9,123,663
App. No.
12/136,682
Granted
Sep 1, 2015
Kind
B2
Abstract

A shielded semiconductor device is made by mounting semiconductor die to a first substrate. An encapsulant is formed over the semiconductor die and first substrate. A dicing channel is formed through the encapsulant between the semiconductor die. A hole is drilled in the first substrate along the dicing channel on each side of the semiconductor die. A shielding layer is formed over the encapsulant and semiconductor die. The hole is lined with the shielding layer. The first substrate is singulated to separate the semiconductor die. The first substrate is mounted to a second substrate. A metal pillar is formed in the opening to electrically connect the shielding layer to a ground plane in the second substrate. The metal pillar includes a hook for a mechanically secure connection to the shielding layer. An interconnect structure is formed on the first substrate to electrically connect the semiconductor die to the second substrate.

Claims (55)

1. A method of making a shielded semiconductor device, comprising:

providing a first substrate, the first substrate including multiple laminated layers;

mounting a plurality of semiconductor die to the first substrate;

forming an encapsulant over the semiconductor die and first substrate;

forming a dicing channel through the encapsulant between the semiconductor die to expose a flat upper surface of the first substrate, the dicing channel having substantially vertical sidewalls;

forming a circular opening through the first substrate and in a region of the flat upper surface that is exposed by the dicing channel;

forming a shielding layer over the encapsulant and in the circular opening, the shielding layer covering sidewalls of the circular opening along an entire length of the circular opening;

singulating the first substrate to separate the semiconductor die;

mounting the first substrate to a second substrate; and

forming a metal pillar in the opening to electrically connect the shielding layer to a ground plane disposed in the second substrate.

2. The method of claim 1 , further including forming an interconnect structure on the first substrate to electrically connect the semiconductor die to the second substrate.

3. The method of claim 1 , wherein the metal pillar includes a hook to make a mechanically secure connection to the shielding layer.

4. The method of claim 1 , further including depositing solder material between the shielding material lining the circular opening and the metal pillar.

5. The method of claim 1 , wherein the circular opening through the first substrate and another circular opening through the first substrate are formed on each side of the semiconductor die.

6. The method of claim 1 , further including drilling a hole in the first substrate to form the circular opening.

7. The method of claim 1 , wherein the shielding layer blocks inter-device interference from the semiconductor die.

8. A method of making a semiconductor device, comprising:

providing a first substrate;

mounting a semiconductor die to the first substrate;

forming an encapsulant over the semiconductor die and first substrate;

forming a dicing channel through the encapsulant in a peripheral region around the semiconductor die to expose a flat upper surface of the first substrate;

forming an opening through the first substrate in a region of the flat upper surface that is exposed by the dicing channel, wherein a perimeter of the opening in a plane of the flat upper surface describes a closed figure;

forming a shielding layer over the encapsulant and in the opening, the shielding layer covering sidewalls of the opening;

mounting the first substrate to a second substrate; and

forming a metal pillar in the opening that electrically connects the shielding layer to a ground plane in the second substrate.

9. The method of claim 8 , further including forming an interconnect structure on the first substrate to electrically connect the semiconductor die to the second substrate.

10. The method of claim 8 , wherein the metal pillar includes a hook to make a mechanically secure connection to the shielding layer.

11. The method of claim 8 , further including depositing solder material between the shielding material lining the opening and metal pillar.

12. The method of claim 8 , wherein the openings in the first substrate are formed in a peripheral region on each side of the semiconductor die.

13. The method of claim 8 , further including drilling a hole in the first substrate to form the opening.

14. A method of making a semiconductor device, comprising:

providing a substrate;

after providing the substrate, mounting a semiconductor die to the substrate;

forming an encapsulant over the semiconductor die and substrate;

forming a dicing channel through the encapsulant in a peripheral region around the semiconductor die to expose an upper surface of the substrate;

forming a shielding layer over the encapsulant; and

forming a metal pillar through a thickness of the shielding layer and through a thickness of the substrate in the peripheral region around the semiconductor die to electrically connect the shielding layer to a ground point.

15. The method of claim 14 , further including:

forming an opening in the substrate along the dicing channel;

lining the opening with the shielding layer; and

forming the metal pillar in the opening.

16. The method of claim 15 , further including depositing solder material between the shielding material lining the opening and metal pillar.

17. The method of claim 15 , wherein the openings in the substrate are formed on each side of the semiconductor die.

18. The method of claim 14 , wherein the metal pillar includes a hook to make a mechanically secure connection to the shielding layer.

19. The method of claim 14 , wherein the shielding layer blocks inter-device interference from the semiconductor die.

20. The method of claim 14 , wherein the shielding layer is selected from the group consisting of copper, aluminum, stainless steel, nickel silver, low-carbon steel, and silicon-iron steel.

21. The semiconductor device of claim 20 , wherein the metal pillars include a hook to make a mechanically secure connection to the shielding layer.

22. The semiconductor device of claim 20 , wherein the metal pillars are formed in a peripheral region on each side of the semiconductor die.

23. The semiconductor device of claim 20 , wherein the shielding layer blocks inter-device interference from the semiconductor die.

24. A semiconductor device, comprising:

a substrate;

a semiconductor die mounted to the substrate;

a molding compound formed over the semiconductor die and the substrate;

a shielding layer formed over the molding compound and the semiconductor die, the shielding layer contacting a sidewall of the substrate along an entire length of the sidewall; and

metal pillars formed through the shielding layer and substrate in a peripheral region around the semiconductor die to electrically connect the shielding layer to a ground point.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039980/0838 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0442 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2008
From: KIM, OHHAN; KIM, SEUNGWON; PARK, JOUNGUN
To: STATS CHIPPAC, LTD.
Reel/Frame 021075/0232 →
Continuity (1)
Related Publication 20090302436A1 · Dec 10, 2009