Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
View Patent ↗A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a substrate;
forming a plurality of conductive traces over the substrate, at least one of the conductive traces including a plurality of interconnect sites;
forming a masking layer over the substrate, the masking layer including a plurality of elongated openings extending over at least two of the conductive traces;
forming an elongated interconnect structure between the semiconductor die and a first interconnect site of the interconnect sites, wherein a length of the elongated interconnect structure along the first interconnect site is greater than a width of the elongated interconnect structure across the first interconnect site, and the width of the elongated interconnect structure is tapered along the length of the elongated interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the first interconnect site; and
depositing an encapsulant between the semiconductor die and substrate.
2. The method of claim 1 , wherein the at least one of the plurality of conductive traces passes beneath at least two of the plurality of elongated openings.
3. The method of claim 1 , wherein a length of each of the plurality of elongated openings is perpendicular to a length of each of the plurality of conductive traces.
4. The method of claim 1 , wherein a width of each of the plurality of elongated openings is less than 90 micrometers.
5. The method of claim 1 , wherein the elongated openings permit a flow of bump material along a length of the plurality of conductive traces within the elongated openings while preventing the flow of bump material past a boundary of the elongated openings.
6. The method of claim 1 , wherein the elongated interconnect structure includes a fusible portion and non-fusible portion.
7. The method of claim 1 , wherein the elongated interconnect structure includes a conductive pillar and bump formed over the conductive pillar.
8. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a substrate;
forming a plurality of conductive traces each including a plurality of interconnect sites over the substrate;
forming a masking layer over the substrate, the masking layer including a plurality of elongated openings formed over at least two of the conductive traces; and
forming an interconnect structure between the semiconductor die and a first interconnect site of the interconnect sites, wherein a length of the interconnect structure along the first interconnect site is greater than a width of the interconnect structure across the first interconnect site, and the width of the interconnect structure is tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the first interconnect site.
9. The method of claim 8 , further including depositing an encapsulant between the semiconductor die and substrate.
10. The method of claim 8 , wherein one of the plurality of conductive traces passes beneath at least two of the plurality of elongated openings.
11. The method of claim 8 , wherein a length of each of the plurality of elongated openings is perpendicular to a length of each of the plurality of conductive traces.
12. The method of claim 8 , wherein a width of each of the plurality of elongated openings is less than 90 micrometers.
13. The method of claim 8 , wherein the interconnect structure includes a fusible portion and non-fusible portion.
14. The method of claim 8 , wherein the interconnect structure includes a conductive pillar and bump formed over the conductive pillar.
15. A semiconductor device, comprising:
a semiconductor die;
a substrate including first and second conductive traces comprising a plurality of interconnect sites formed over a surface of the substrate;
a masking layer formed over the surface of the substrate, the masking layer including first and second elongated openings each formed over interconnect sites of the first and second conductive traces;
an elongated interconnect structure formed between the semiconductor die and a first interconnect site of the interconnect sites and over a top surface and side surface of the first interconnect site, wherein a length of the elongated interconnect structure along the first interconnect site is greater than a width of the elongated interconnect structure across the first interconnect site, and the width of the elongated interconnect structure is tapered along the length of the elongated interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the first interconnect site; and
an encapsulant deposited between the semiconductor die and substrate.
16. The semiconductor device of claim 15 , wherein the first and second conductive traces pass beneath the first and second elongated openings.
17. The semiconductor device of claim 15 , wherein a length of the first and second elongated openings is perpendicular to a length of the first and second conductive traces.
18. The semiconductor device of claim 15 , wherein the elongated interconnect structure includes a fusible portion and non-fusible portion.
19. The semiconductor device of claim 15 , wherein the elongated interconnect structure includes a conductive pillar and bump formed over the conductive pillar.
20. A semiconductor device, comprising:
a semiconductor die;
a substrate;
a plurality of conductive traces formed over the substrate, a first conductive trace of the conductive traces including a plurality of interconnect sites;
a masking layer formed over the substrate, the masking layer including a plurality of elongated openings extending over at least two of the conductive traces;
an interconnect structure formed between the semiconductor die and a first interconnect site of the interconnect sites, wherein a length of the interconnect structure along the first interconnect site is greater than a width of the interconnect structure across the first interconnect site, and the width of the interconnect structure is tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the first interconnect site; and
an encapsulant deposited between the semiconductor die and substrate.
21. The semiconductor device of claim 20 , wherein at least one of the plurality of conductive traces passes beneath at least two of the plurality of elongated openings.
22. The semiconductor device of claim 20 , wherein a length of each of the plurality of elongated openings is perpendicular to a length of each of the plurality of conductive traces.
23. The semiconductor device of claim 20 , wherein a width of each of the plurality of elongated openings is less than 90 micrometers.
24. The semiconductor device of claim 20 , wherein the elongated openings permit a flow of bump material along a length of the plurality of conductive traces within the elongated openings while preventing the flow of bump material past a boundary of the elongated openings.
25. The semiconductor device of claim 20 , wherein the interconnect structure includes a fusible portion and non-fusible portion.
26. A semiconductor device, comprising:
a semiconductor die;
a substrate;
a plurality of conductive traces each including a plurality of interconnect sites formed over the substrate;
a masking layer formed over the substrate, the masking layer including a plurality of elongated openings formed over at least two of the conductive traces; and
an interconnect structure formed between the semiconductor die and a first interconnect site of the interconnect sites, wherein a length of the interconnect structure along the first interconnect site is greater than a width of the interconnect structure across the first interconnect site, and the width of the interconnect structure is tapered along the length of the interconnect structure to be wider proximate to the semiconductor die and narrower proximate to the first interconnect site.
27. The semiconductor device of claim 26 , further including an encapsulant deposited around the interconnect structure.
28. The semiconductor device of claim 26 , wherein one of the plurality of conductive traces passes beneath at least two of the plurality of elongated openings.
29. The semiconductor device of claim 26 , wherein a length of each of the plurality of elongated openings is perpendicular to a length of each of the plurality of conductive traces.
30. The semiconductor device of claim 26 , wherein the interconnect structure includes a conductive pillar and bump formed over the conductive pillar.