IP Library Granted Patent US 9,224,647
Granted Patent B2
US 9,224,647 · App. 13/184,253 · Granted Dec 29, 2015

Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer

Inventors: Jun Mo Koo (Singapore, SG); Pandi Chelvam Marimuthu (Singapore, SG); Jae Hun Ku (Singapore, SG); Seung Wook Yoon (Singapore, SG)
Assignee: STATS ChipPAC, Ltd.
H01L21/76898H01L21/486H01L21/561H01L21/568H01L23/147H01L23/49827H01L23/49833H01L25/0652H01L25/0655H01L25/0657H01L25/105H01L25/50H01L23/3128H01L23/49816H01L24/05H01L24/06H01L24/13H01L24/16H01L24/73H01L24/81H01L24/92H01L24/97H01L25/18H01L2224/0345H01L2224/03452H01L2224/03464H01L2224/0401H01L2224/05009H01L2224/0557H01L2224/05611H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/06181H01L2224/13111H01L2224/13113H01L2224/13116H01L2224/13124H01L2224/13139H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/16145H01L2224/16146H01L2224/16225H01L2224/16227H01L2224/16235H01L2224/32225H01L2224/48091H01L2224/73204H01L2224/73265H01L2224/81192H01L2224/81201H01L2224/81411H01L2224/81424H01L2224/81439H01L2224/81444H01L2224/81447H01L2224/81455H01L2224/81815H01L2224/92125H01L2224/97H01L2225/06513H01L2225/06517H01L2225/06541H01L2225/06548H01L2225/1023H01L2225/1058H01L2924/00014H01L2924/01322H01L2924/12041H01L2924/13091H01L2924/1431H01L2924/1433H01L2924/1434H01L2924/14335H01L2924/15311H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105H01L2924/3511
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Quick Facts
Patent No.
US 9,224,647
App. No.
13/184,253
Granted
Dec 29, 2015
Kind
B2
Abstract

A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die.

Claims (34)

1. A method of making a semiconductor device, comprising:

providing a substrate including first and second opposing surfaces;

forming a plurality of vias partially through the first surface of the substrate;

completely filling the plurality of vias with a conductive material to form a plurality of conductive vias;

forming a conductive layer over the first surface of the substrate electrically connected to the conductive vias;

disposing an insulating layer around the conductive layer to completely cover side surfaces of the conductive layer;

disposing a first semiconductor die over the first surface of the substrate electrically connected to the conductive layer;

depositing an encapsulant over the first semiconductor die and substrate including a side surface of the substrate;

removing a portion of the second surface of the substrate to expose the conductive vias coplanar with the second surface of the substrate after disposing the first semiconductor die over the substrate;

forming a redistribution layer over the encapsulant and substrate opposite the first semiconductor die and electrically connected to the first semiconductor die; and

forming a conductive via through the encapsulant and electrically connected to the redistribution layer.

2. The method of claim 1 , further including:

forming the insulating layer prior to disposing the first semiconductor die over the first surface of the substrate; and

forming a plurality of bumps over the conductive layer.

3. The method of claim 1 , further including depositing an underfill material beneath the first semiconductor die.

4. The method of claim 1 , further including disposing a second semiconductor die over the first semiconductor die.

5. The method of claim 1 , further including disposing a plurality of second semiconductor die over the first semiconductor die.

6. The method of claim 1 , further including disposing a second semiconductor die over the first surface of the substrate adjacent to the first semiconductor die.

7. The method of claim 1 , further including forming an interconnect structure over the second surface of the substrate.

8. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive via within the substrate;

forming a conductive layer, including a redistribution layer and a second conductive via, over the first conductive via;

forming an insulating layer over the substrate after forming the redistribution layer and second conductive via;

disposing a first semiconductor die over the substrate;

disposing an encapsulant over the semiconductor die and substrate including a side surface of the substrate;

removing a portion of the substrate to expose the first conductive via; and

forming a build-up interconnect structure over the exposed first conductive via, encapsulant, and first semiconductor die.

9. The method of claim 8 , further including forming the first conductive via partially through a first surface of the substrate.

10. The method of claim 8 , further including forming an interconnect structure over the substrate opposite the first semiconductor die.

11. The method of claim 8 , further including disposing a second semiconductor die over the first semiconductor die.

12. The method of claim 8 , further including forming a third conductive via through the first semiconductor die.

13. The method of claim 8 , further including disposing a second semiconductor die including a memory circuit over the first semiconductor die.

14. The method of claim 8 , further including disposing a second semiconductor die over a first surface of the substrate adjacent to the first semiconductor die.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053511/0298 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0427 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2011
From: KOO, JUN MO; MARIMUTHU, PANDI CHELVAM; KU, JAE HUN; YOON, SEUNG WOOK
To: STATS CHIPPAC, LTD.
Reel/Frame 026601/0617 →
Continuity (2)
Provisional Application 61386423 · Sep 24, 2010
Related Publication 20120074585A1 · Mar 29, 2012