Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution
A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.
1 . A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of contact pads formed over a surface of the semiconductor wafer;
forming a first insulating layer over the semiconductor wafer;
forming a first multilayer metallization pattern over the first insulating layer electrically connected to two or more of the contact pads;
forming a common bus over the first multilayer metallization pattern;
forming a second insulating layer over the first insulating layer and common bus; and
forming a plurality of bumps over the common bus.
2 . The method of claim 1 , further including forming a plurality of conductive pillars over the common bus.
3 . The method of claim 2 , further including forming a second multilayer metallization pattern over the common bus prior to forming the conductive pillars.
4 . The method of claim 1 , wherein forming the first multilayer metallization pattern includes:
forming an adhesion layer over the first insulating layer;
forming a barrier layer over the adhesion layer; and
forming a seed layer over the barrier layer.
5 . The method of claim 1 , further including forming a second multilayer metallization pattern over the common bus prior to forming the bumps.
6 . The method of claim 1 , wherein the first insulating layer reduces stress on the semiconductor wafer.
7 . A method of making a semiconductor device, comprising:
providing a semiconductor die including a plurality of contact pads formed over a surface of the semiconductor die;
forming a first insulating layer over the semiconductor die;
forming a first metallization pattern over the first insulating layer electrically connected to two or more of the contact pads; and
forming a common bus over the first metallization pattern.
8 . The method of claim 7 , further including:
forming a second insulating layer over the first insulating layer and common bus; and
forming a bump over the common bus.
9 . The method of claim 8 , further including forming a second metallization pattern over the common bus prior to forming the bump.
10 . The method of claim 7 , further including forming a conductive pillar over the common bus.
11 . The method of claim 10 , further including forming a second metallization pattern over the common bus prior to forming the conductive pillar.
12 . The method of claim 7 , wherein forming the first metallization pattern includes:
forming an adhesion layer over the first insulating layer;
forming a barrier layer over the adhesion layer; and
forming a seed layer over the barrier layer.
13 . The method of claim 7 , wherein the first insulating layer reduces stress on the semiconductor wafer.
14 . A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a first metallization pattern over the semiconductor die electrically connected to two or more contact points on the semiconductor die; and
forming a common bus over the first metallization pattern.
15 . The method of claim 14 , further including forming an insulating layer over the semiconductor die prior to forming the first metallization pattern.
16 . The method of claim 14 , further including forming a bump over the common bus.
17 . The method of claim 16 , further including forming a second metallization pattern over the common bus prior to forming the bump.
18 . The method of claim 14 , further including forming a conductive pillar over the common bus.
19 . The method of claim 18 , further including forming a second metallization pattern over the common bus prior to forming the conductive pillar.
20 . The method of claim 14 , wherein forming the first metallization pattern includes:
forming an adhesion layer over the semiconductor die;
forming a barrier layer over the adhesion layer; and
forming a seed layer over the barrier layer.
21 . A semiconductor device, comprising:
a semiconductor die including a plurality of contact pads formed over a surface of the semiconductor die;
a first insulating layer formed over the semiconductor die;
a first metallization pattern formed over the first insulating layer electrically connected to two or more of the contact pads; and
a common bus formed over the first metallization pattern.
22 . The semiconductor device of claim 21 , further including:
a second insulating layer formed over the first insulating layer and common bus; and
a bump formed over the common bus.
23 . The semiconductor device of claim 21 , further including a conductive pillar formed over the common bus.
24 . The semiconductor device of claim 21 , further including a second metallization pattern formed over the common bus.
25 . The semiconductor device of claim 21 , wherein the first insulating layer reduces stress on the semiconductor wafer.