Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
A semiconductor device has a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area. An underfill material is deposited between the semiconductor die and substrate. The semiconductor die includes a flexible property. The vertical interconnect structure includes a flexible property. The substrate includes a flexible property.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a substrate;
forming a vertical interconnect structure including a linear sidewall extending from the semiconductor die to the substrate; and
mounting the semiconductor die to the substrate including a fixed offset between the semiconductor die and substrate, wherein a first width of the vertical interconnect structure in a cross-section taken perpendicular to the linear sidewall is greater than a second width of the vertical interconnect structure in the cross-section of the first width of the vertical interconnect structure prior to mounting the semiconductor die to the substrate.
2. The method of claim 1 , wherein the vertical interconnect structure includes a stud bump or conductive column.
3. The method of claim 1 , wherein the vertical interconnect structure includes copper.
4. The method of claim 1 , wherein the vertical interconnect structure includes a tapered sidewall.
5. The method of claim 1 , wherein a width of the vertical interconnect structure is greater than a mating conductive trace formed on the semiconductor die or substrate.
6. The method of claim 1 , wherein the vertical interconnect structure includes an oval cross sectional area.
7. The method of claim 1 , wherein the semiconductor die includes a flexible property, the vertical interconnect structure includes a flexible property, and the substrate includes a flexible property.