Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure
A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.
1. A semiconductor device, comprising:
a first conductive layer;
a vertical interconnect structure disposed over the first conductive layer;
a no-flow insulating material disposed around the vertical interconnect structure and the first conductive layer;
a first semiconductor die embedded within the no-flow insulating material over the first conductive layer, wherein the no-flow insulating material, first semiconductor die, and vertical interconnect structure includes a planar surface and the first conductive layer is partially embedded in the no-flow insulating material to cover a side surface of the first conductive layer;
a first interconnect structure formed over the planar surface, the first interconnect structure including a second conductive layer formed in direct contact with the vertical interconnect structure and a surface of the no-flow insulating material and extending over the surface of the no-flow insulating material outside a contact interface between the first interconnect structure and the vertical interconnect structure;
a second semiconductor die disposed over the first interconnect structure and directly overlying the first semiconductor die, wherein the second semiconductor die is a duplicate of the first semiconductor die; and
a second interconnect structure formed over and contacting the first conductive layer opposite the first interconnect structure.
2. The semiconductor device of claim 1 , wherein the first interconnect structure or second interconnect structure includes an integrated passive device.
3. The semiconductor device of claim 1 , further including a plurality of stacked semiconductor devices.
4. The semiconductor device of claim 1 , wherein the vertical interconnect structure includes a bump.
5. The semiconductor device of claim 1 , wherein the first interconnect structure or second interconnect structure includes an insulating layer.