Semiconductor device and method of forming wafer level ground plane and power ring
A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant around a peripheral area of the semiconductor die to form a die extension region;
forming a plurality of conductive vias through the encapsulant in the die extension region;
forming a conductive plane over the semiconductor die and electrically connected to a first one of the conductive vias; and
forming a conductive ring over the semiconductor die and electrically connected to a second one of the conductive vias.
2. The method of claim 1 , further including coupling the conductive plane and conductive ring to the conductive vias.
3. The method of claim 1 , further including forming the conductive plane over an active surface of the semiconductor die.
4. The method of claim 1 , further including coupling the conductive plane or conductive ring to a contact pad of the semiconductor die.
5. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited around a peripheral area of the semiconductor die to form a die extension region;
a first conductive via disposed through the encapsulant in the die extension region;
a conductive plane formed over the semiconductor die and coupled to the first conductive via;
a second conductive via disposed through the encapsulant in the die extension region; and
a conductive ring formed over the semiconductor die and coupled to the second conductive via.
6. The semiconductor device of claim 5 , further including:
a conductive layer formed over the semiconductor die; and
a plurality of bumps formed over the conductive layer.
7. The semiconductor device of claim 5 , further including an insulation layer formed between the semiconductor die and the conductive plane.
8. The semiconductor device of claim 5 , wherein the conductive plane provides a first power supply potential to the semiconductor die and the conductive ring provides a second power supply potential to the semiconductor die.
9. The semiconductor device of claim 5 , wherein the conductive plane is formed over an active surface of the semiconductor die.
10. The semiconductor device of claim 5 , further including a heat sink disposed over the conductive plane.
11. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing a molding compound in a die extension region around a peripheral area outside a footprint of the semiconductor die;
forming a first conductive via and second conductive via through the molding compound in the die extension region;
forming a conductive plane over the semiconductor die and electrically connected to the semiconductor die and first conductive via; and
forming a conductive ring over the semiconductor die and electrically connected to the semiconductor die and second conductive via.
12. The method of claim 11 , further including forming a first conductive layer over the semiconductor die.
13. The method of claim 11 , further including forming a conductive layer over the semiconductor die opposite the conductive plane.
14. The method of claim 11 , wherein the conductive plane provides a first power supply potential to the semiconductor die and the conductive ring provides a second power supply potential to the semiconductor die.
15. The method of claim 11 , further including forming the conductive plane over an active surface of the semiconductor die.
16. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing a molding compound in a peripheral region of the semiconductor die to form a die extension region;
forming a plurality of conductive vias in the die extension region;
forming a conductive plane over an active surface of the semiconductor die to connect to a first contact pad on the active surface and a first conductive via of the plurality of conductive vias; and
forming a conductive ring partially around a perimeter of the conductive plane to connect to a second contact pad on the active surface and a second conductive via of the plurality of conductive vias, wherein the semiconductor device includes a wafer level chip scale package.
17. The method of claim 16 , further including forming a conductive layer over a surface of the semiconductor die opposite the active surface and in electrical contact with the plurality of conductive vias.
18. The method of claim 16 , further including forming the plurality of conductive vias into a first row of conductive vias and a second row of conductive vias offset from the first row of conductive vias.
19. The method of claim 16 , wherein the conductive plane provides a first power supply potential to the semiconductor die and the conductive ring provides a second power supply potential to the semiconductor die.
20. The method of claim 16 , further including:
forming an under bump metallization over the conductive plane; and
forming a bump on the under bump metallization.
21. The method of claim 16 , wherein the conductive plane is formed over a center area of the active surface of the semiconductor die.