IP Library › Assignment 052850/0237
Patent Assignment
Reel/Frame 052850/0237

RELEASE OF SECURITY INTEREST

Recorded: 2020-06-05 Received: 2020-06-05 Pages: 31
Assignor
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications (100)
Bump-On-Lead Flip Chip Interconnection
App. No. 13/756,779
→
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 13/756,905
→
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
App. No. 13/756,679
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
App. No. 13/752,157
→
METHOD OF FORMING A BUMP-ON-LEAD FLIP CHIP INTERCONNECTION HAVING HIGHER ESCAPE ROUTING DENSITY
App. No. 13/750,975
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AIR GAP ADJACENT TO STRESS SENSITIVE REGION OF THE DIE
App. No. 13/706,818
→
SEMICONDUCTOR DEVICE INCLUDING BUMP FORMED ON SUBSTRATE TO PREVENT EXTRIMELY-LOW DIELECTRIC CONSTANT (ELK) INTERLAYER DIELECTRIC LAYER (ILD) DELAMINATION DURING REFLOW PROCESS
App. No. 13/691,427
→
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/679,615
→
Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures
App. No. 13/615,308
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PARTIALLY-ETCHED CONDUCTIVE LAYER RECESSED WITHIN SUBSTRATE FOR BONDING TO SEMICONDUCTOR DIE
App. No. 13/606,631
→
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
App. No. 13/558,586
→
Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
App. No. 13/559,430
→
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
App. No. 13/558,953
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 13/556,106
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 13/556,064
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/542,120
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDING SPACER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/531,941
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TIEBAR-LESS DESIGN AND METHOD OF MANUFACTURE THEREOF
App. No. 13/523,261
→
APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
App. No. 13/492,646
→
LEADFRAME-BASED MOLD ARRAY PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
App. No. 13/492,765
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKABLE DEVICES AND A METHOD OF MANUFACTURE THEREOF
App. No. 13/477,630
→
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
App. No. 13/476,899
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 13/464,979
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MOLD UNDERFILL USING DISPENSING NEEDLE HAVING SAME WIDTH AS SEMICONDUCTOR DIE
App. No. 13/458,289
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STUD BUMPS OVER EMBEDDED DIE
App. No. 13/441,691
→
THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
App. No. 13/438,155
→
METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/431,816
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/426,442
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND LEADFRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
App. No. 13/425,277
→
SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
App. No. 13/423,739
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE
App. No. 13/423,832
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
App. No. 13/423,263
→
Semiconductor Device and Method of Forming With Three-Dimensional Vertically Oriented Integrated Capacitors
App. No. 13/421,770
→
OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
App. No. 13/419,242
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
App. No. 13/417,034
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SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS IN PERIPHERAL REGION CONNECTING SHIELDING LAYER TO GROUND
App. No. 13/360,549
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/326,891
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSISTANCE MOLD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/327,091
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/326,728
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/326,090
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/325,903
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/326,173
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER INTERCONNECTIONS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/324,380
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SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
App. No. 13/314,984
→
METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT
App. No. 13/300,088
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT
App. No. 13/272,034
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/269,442
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON DIFFERENT HEIGHT TRACES
App. No. 13/268,091
→
INTEGRATED CIRCUIT SYSTEM WITH TEST PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/239,373
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A COMPONENT IN AN ENCAPSULANT CAVITY AND METHOD OF FABRICATION THEREOF
App. No. 13/235,755
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE UNDERLAYER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/235,135
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE MOLD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/235,202
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SEMICONDUCTOR DEVICE WITH CONDUCTIVE VIAS BETWEEN SAW STREETS
App. No. 13/228,248
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SEMICONDUCTOR DEVICE AND METHOD OF CONFORMING CONDUCTIVE VIAS BETWEEN INSULATING LAYERS IN SAW STREETS
App. No. 13/228,226
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STIFFENER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/224,725
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED THERMAL HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/224,718
→
Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage
App. No. 13/223,478
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NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES
App. No. 13/215,131
→
SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/211,698
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
App. No. 13/209,620
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/197,122
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LAMINATE BASE
App. No. 13/196,279
→
SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURING THEREOF
App. No. 13/194,874
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE MATERIAL OVER SEMICONDUCTOR DIE AND CARRIER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
App. No. 13/185,384
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND AXIS
App. No. 13/181,290
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED ENCAPSULATION AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/178,347
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Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
App. No. 13/174,033
→
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/169,387
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/164,114
→
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
App. No. 13/164,015
→
METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE
App. No. 13/163,643
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTRA SUBSTRATE DIE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/162,513
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE ON PACKAGE SUPPORT AND METHOD OF MANUFACTURE THEREOF
App. No. 13/162,526
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METHOD FOR MANUFACTURING WAFER SCALE HEAT SLUG SYSTEM
App. No. 13/161,008
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/161,368
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/160,799
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METHOD FOR MANUFACTURE OF INLINE INTEGRATED CIRCUIT SYSTEM
App. No. 13/159,095
→
INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/154,308
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 13/118,955
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
App. No. 13/149,669
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/118,310
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF
App. No. 13/118,214
→
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/112,717
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 13/105,814
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/102,041
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL
App. No. 13/100,235
→
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/095,680
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METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS
App. No. 13/081,227
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/081,011
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,514
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,760
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LOCKING INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,433
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,899
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,789
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,449
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COLLAPSED MULTI-INTEGRATION PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,397
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CONDUCTIVE STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,219
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIPCHIP LEADFRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,291
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/053,719
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/053,142
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