IP Library Granted Patent US 8,492,204
Granted Patent B2
US 8,492,204 · App. 13/081,011 · Granted Jul 23, 2013

Integrated circuit package-in-package system with wire-in-film encapsulant and method for manufacturing thereof

Inventors: Byung Tai Do (Singapore, SG); Seng Guan Chow (Singapore, SG); Heap Hoe Kuan (Singapore, SG); Linda Pei Ee Chua (Singapore, SG); Rui Huang (Singapore, SG)
Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,492,204
App. No.
13/081,011
Granted
Jul 23, 2013
Kind
B2
Abstract

A method for manufacturing a multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die.

Claims (41)

1. A method for manufacturing a multiple encapsulation integrated circuit package-in-package system comprising;

dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant;

positioning internal leadfingers adjacent and connected to a bottom integrated circuit die;

pressing the bottom encapsulant on to the bottom integrated circuit die;

connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and

forming a top encapsulant over the top integrated circuit die.

2. The method as claimed in claim 1 wherein forming the top encapsulant includes:

placing the top encapsulant over a stiffener; and

pressing the stiffener and the top encapsulant over the top integrated circuit die.

3. The method as claimed in claim 1 wherein forming the top encapsulant includes:

molding a mold compound around the around the top integrated circuit die, the bottom encapsulant and the internal leadfingers.

4. The method as claimed in claim 1 further comprising.

positioning the bottom integrated circuit die, the internal lead fingers, and the external lead fingers on a carrier before pressing the bottom encapsulant on to the bottom integrated circuit die;

removing the carrier; and

dicing the top encapsulant, the bottom encapsulant, and the external leadfingers.

5. The method as claimed in claim 1 wherein placing the internal leadfingers includes:

placing a die attach paddle among the internal leadfingers; and

mounting the bottom integrated circuit on the die attach paddle.

6. A method for manufacturing a multiple encapsulation integrated circuit package-in-package system comprising:

bonding a bottom encapsulant on to a top integrated circuit wafer;

dicing the top integrated circuit wafer with the bottom encapsulant to form a top integrated circuit die with the bottom encapsulant;

positioning internal leadfingers adjacent and connected to a bottom integrated circuit die;

placing external leadfingers adjacent the internal leadfingers;

pressing the top die with the bottom encapsulant on to the bottom integrated circuit die to form a bottom package;

curing the bottom encapsulant;

connecting the top integrated circuit die to the external leadfingers; and

forming a top encapsulant over the top integrated circuit die and the external leadfingers.

7. The method as claimed in claim 6 wherein forming the top encapsulant includes:

placing an adhesive layer on a stiffener;

placing a buffer layer on the adhesive layer;

placing the top encapsulant on the buffer layer;

pressing the stiffener down on the top integrated circuit die to encapsulate the bottom package; and

curing the top encapsulant.

8. The method as claimed in claim 6 wherein:

pressing the top die with the bottom encapsulant on to the bottom integrated circuit die leaves a portion of the internal leadfingers extending from the bottom encapsulant; and

interconnecting the internal leadfingers and the external leadfingers.

9. The method as claimed in claim 6 wherein forming the top encapsulant includes:

placing a heat sink having a protrusion over the bottom package with the protrusion adjacent the top integrated circuit die.

10. The method as claimed in claim 6 wherein:

pressing the top die with the bottom encapsulant on to the bottom integrated circuit die leaves the bottom of the internal leadfingers protruding; and

forming the top encapsulant over the external leadfingers leaves the bottom of the external leadfingers protruding.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Continuity (3)
Continuation 12121752 · May 15, 2008
Provisional Application 60988724 · Nov 16, 2007
Related Publication 20110180914A1 · Jul 28, 2011