Patent Assignment
Reel/Frame 038378/0235
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 9
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(81)
METHOD OF FORMING A BUMP-ON-LEAD FLIP CHIP INTERCONNECTION HAVING HIGHER ESCAPE ROUTING DENSITY
App. No. 13/750,975
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PARTIALLY-ETCHED CONDUCTIVE LAYER RECESSED WITHIN SUBSTRATE FOR BONDING TO SEMICONDUCTOR DIE
App. No. 13/606,631
→
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
App. No. 13/558,586
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 13/556,106
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 13/556,064
→
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
App. No. 13/476,899
→
SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
App. No. 13/423,739
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE
App. No. 13/423,832
→
Semiconductor Device and Method of Forming With Three-Dimensional Vertically Oriented Integrated Capacitors
App. No. 13/421,770
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED EMI SHIELDING FRAME WITH CAVITIES CONTAINING PENETRABLE MATERIAL OVER SEMICONDUCTOR DIE
App. No. 13/349,919
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
App. No. 13/333,739
→
PHOTOCHROMIC COMPOUNDS AND COMPOSITIONS
App. No. 13/325,285
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/326,173
→
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
App. No. 13/314,984
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECONSTITUTED WAFER WITH LARGER CARRIER TO ACHIEVE MORE EWLB PACKAGES PER WAFER WITH ENCAPSULANT DEPOSITED UNDER TEMPERATURE AND PRESSURE
App. No. 13/295,843
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT
App. No. 13/272,034
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/269,442
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE UNDERLAYER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/235,135
→
SEMICONDUCTOR DEVICE WITH CONDUCTIVE VIAS BETWEEN SAW STREETS
App. No. 13/228,248
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFORMING CONDUCTIVE VIAS BETWEEN INSULATING LAYERS IN SAW STREETS
App. No. 13/228,226
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STIFFENER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/224,725
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE MATERIAL OVER SEMICONDUCTOR DIE AND CARRIER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
App. No. 13/185,384
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND AXIS
App. No. 13/181,290
→
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
App. No. 13/164,015
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTRA SUBSTRATE DIE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/162,513
→
METHOD FOR MANUFACTURE OF INLINE INTEGRATED CIRCUIT SYSTEM
App. No. 13/159,095
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/118,310
→
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/112,717
→
WIREBONDLESS WAFER LEVEL PACKAGE WITH PLATED BUMPS AND INTERCONNECTS
App. No. 13/101,657
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL
App. No. 13/100,235
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/081,011
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,789
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/053,096
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/048,859
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER AND OPPOSING BUILD-UP INTERCONNECT STRUCTURE WITH CONNECTING CONDUCTIVE TMV FOR ELECTRICAL INTERCONNECT OF FO-WLCSP
App. No. 13/035,669
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP
App. No. 13/023,244
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/017,170
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INDUCTOR WITHIN INTERCONNECT LAYER VERTICALLY SEPARATED FROM SEMICONDUCTOR DIE
App. No. 12/964,810
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/964,617
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION SUPPORTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/957,361
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-ROW LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/957,339
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH RECESSES FOR CAPTURING BUMPED SEMICONDUCTOR DIE
App. No. 12/953,812
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FOLDABLE SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/948,756
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF
App. No. 12/890,338
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ACTIVE SURFACE HEAT REMOVAL AND METHOD OF MANUFACTURE THEREOF
App. No. 12/887,681
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST AND METHOD OF MANUFACTURE THEREOF
App. No. 12/885,137
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/884,134
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BOND-ON-LEAD INTERCONNECTION FOR MOUNTING SEMICONDUCTOR DIE IN FO-WLCSP
App. No. 12/880,255
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/875,496
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE
App. No. 12/874,827
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV SEMICONDUCTOR WAFER WITH EMBEDDED SEMICONDUCTOR DIE
App. No. 12/874,787
→
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-Up Interconnect Structure
App. No. 12/871,401
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET CONDUCTIVE PILLARS OVER FIRST SUBSTRATE ALIGNED TO VERTICALLY OFFSET BOT INTERCONNECT SITES FORMED OVER SECOND SUBSTRATE
App. No. 12/858,163
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHAPED LEAD AND METHOD OF MANUFACTURE THEREOF
App. No. 12/856,288
→
SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
App. No. 12/813,315
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/789,203
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/789,077
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EMBEDDED DIE SUPERSTRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/787,216
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/785,951
→
INTEGRATED CIRCUIT HEAT SPREADER STACKING SYSTEM
App. No. 12/781,772
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
App. No. 12/775,324
→
SOLDER BUMP CONFINEMENT SYSTEM FOR AN INTEGRATED CIRCUIT PACKAGE
App. No. 12/756,067
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 12/731,472
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLEX TAPE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/717,085
→
CIRCUIT SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/716,271
→
SEMICONDUCTOR PACKAGING SYSTEM WITH AN ALIGNED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/710,359
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/639,997
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 12/489,122
→
INTEGRATED CIRCUIT SYSTEM HAVING DIFFERENT-SIZE SOLDER BUMPS AND DIFFERENT-SIZE BONDING PADS
App. No. 12/484,099
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACK PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/484,158
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/193,540
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BUMPED LEAD AND NONBUMPED LEAD
App. No. 12/168,803
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTENDED CORNER LEADS
App. No. 11/965,550
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD
App. No. 11/952,968
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTERNAL INTERCONNECTS AT HIGH DENSITY
App. No. 11/856,841
→
PACKAGING SYSTEM WITH HOLLOW PACKAGE AND METHOD FOR THE SAME
App. No. 11/769,520
→
PACKAGE-IN-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
App. No. 11/768,825
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH L-SHAPED LEADFINGERS
App. No. 11/677,487
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING A SUPPORT STRUCTURE WITH A RECESS
App. No. 11/610,401
→
STACKABLE MULTI-CHIP PACKAGE SYSTEM
App. No. 11/462,607
→
INTEGRATED CIRCUIT LEADED STACKED PACKAGE SYSTEM
App. No. 11/276,645
→