Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant over a first surface of the semiconductor die and around a peripheral region of the semiconductor die;

forming a first insulating layer in direct contact with a second surface of the semiconductor die opposite the first surface of the semiconductor die and over the encapsulant, wherein a coefficient of thermal expansion (CTE) of the first insulating layer is within a first range;

curing the first insulating layer with multiple dwell cycles to enhance adhesion to the semiconductor die and encapsulant;

forming a first conductive layer over the first insulating layer;

forming a second insulating layer in direct contact with the first insulating layer and first conductive layer, wherein a CTE of the second insulating layer is within a second range which is less than the first range and non-overlapping with the first range;

curing the second insulating layer with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer; and

forming a third insulating layer in direct contact with the second insulating layer, wherein a CTE of the third insulating layer is within a third range which is less than the first and second ranges and non-overlapping with the second range.

2. The method of claim 1 , wherein the multiple dwell cycles include a first dwell step with a first temperature for a first time period, second dwell step with a second temperature for a second time period, and third dwell step with a third temperature for a third time period.

3. The method of claim 1 , further including

forming a second conductive layer over the second insulating layer and first conductive layer.

4. The method of claim 3 , further including curing the third insulating layer with multiple dwell cycles to a dense state to block moisture.

5. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant over a first surface of the semiconductor die;

forming a first insulating layer in direct contact with a second surface of the semiconductor die opposite the first surface of the semiconductor die, wherein a coefficient of thermal expansion (CTE) of the first insulating layer is within a first range;

forming a first conductive layer over the first insulating layer;

forming a second insulating layer in direct contact with the first insulating layer and first conductive layer, wherein a CTE of the second insulating layer is within a second range which is less than the first range and non-overlapping with the first range; and

forming a third insulating layer in direct contact with the second insulating layer, wherein a CTE of the third insulating layer is within a third range which is less than the second range and non-overlapping with the second range.

6. The method of claim 5 , further including:

curing the first insulating layer with multiple dwell cycles to enhance adhesion to the semiconductor die; and

curing the second insulating layer with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer.

7. The method of claim 6 , wherein the multiple dwell cycles include a first dwell step with a first temperature for a first time period, second dwell step with a second temperature for a second time period, and third dwell step with a third temperature for a third time period.

8. The method of claim 5 , further including

forming a second conductive layer over the second insulating layer and first conductive layer.

9. The method of claim 8 , further including curing the third insulating layer with multiple dwell cycles to block moisture.

10. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first insulating layer in direct contact with the semiconductor die, wherein a coefficient of thermal expansion (CTE) of the first insulating layer is within a first range;

curing the first insulating layer with multiple dwell cycles including a first dwell step at a temperature less than 100° C.;

forming a first conductive layer over the first insulating layer; and

forming a second insulating layer in direct contact with the first insulating layer and first conductive layer, wherein a CTE of the second insulating layer is within a second range which is less than the first range and non-overlapping with the first range; and

forming a third insulating layer in direct contact with the second insulating layer, wherein a CTE of the third insulating layer is within a third range which is less than the second range and non-overlapping with the second range.

11. The method of claim 10 , further including

depositing an encapsulant over a first surface of the semiconductor die; and

forming the first insulating layer over a second surface of the semiconductor die opposite the first surface of the semiconductor die.

12. The method of claim 10 , further including

forming a second conductive layer over the second insulating layer and first conductive layer.

13. The method of claim 10 , further including curing the second insulating layer with multiple dwell cycles.