Wirebondless wafer level package with plated bumps and interconnects
A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip.
1. A semiconductor package,
comprising:
a substrate including a die cavity and a plurality of bump cavities formed partially through the substrate;
a first semiconductor die disposed in the die cavity of the substrate;
a conductive layer disposed over the substrate to form a package bump within the bump cavities and an interconnect between the package bump and a contact pad of the first semiconductor die; and
an encapsulant deposited over the substrate and conductive layer and into the bump cavities.
2. The semiconductor package of claim 1 , further comprising:
an underfill material disposed in the die cavity between the first semiconductor die and substrate; and
a passivation layer disposed over the first semiconductor die.
3. The semiconductor package of claim 1 , further comprising a conductive bump deposited over the package bump.
4. The semiconductor package of claim 1 , further comprising:
a second semiconductor die disposed over the first semiconductor die; and
a wirebond disposed between a contact pad of the second semiconductor die and the package bump.
5. The semiconductor package of claim 1 , wherein the conductive layer comprises a plurality of layers of conductive material.
6. The semiconductor package of claim 1 , further comprising a passivation layer disposed over the semiconductor package.
7. A semiconductor package,
comprising:
a substrate including a die cavity and a bump cavity;
a semiconductor die disposed in the die cavity of the substrate;
a first conductive layer disposed within the bump cavity to form a package bump; and
an encapsulant deposited over the substrate and first conductive layer and into the bump cavity.
8. The semiconductor package of claim 7 , wherein the first conductive layer comprises a plurality of layers of conductive material.
9. The semiconductor package of claim 7 , wherein the package bump and the contact pad of the semiconductor die are connected by a single layer of conductive material.
10. The semiconductor package of claim 7 , further including a second conductive layer electrically connecting the package bump and the semiconductor die.
11. The semiconductor package of claim 7 , further including a die attach adhesive for mounting the semiconductor die in the die cavity of the substrate.
12. A semiconductor package,
comprising:
a substrate including a die cavity and a bump cavity;
a semiconductor die disposed in the die cavity of the substrate;
a bump layer disposed within the bump cavity; and
an encapsulant deposited over the substrate and bump layer and into the bump cavity.
13. The semiconductor package of claim 12 , further comprising an underfill material disposed in the die cavity between the semiconductor die and substrate.
14. The semiconductor package of claim 12 , further comprising a conductive layer formed over the substrate electrically connecting the package bump and semiconductor die.
15. The semiconductor package of claim 14 , wherein the conductive layer comprises a plurality of layers of conductive material.
16. The semiconductor package of claim 12 , further comprising a passivation layer disposed over the semiconductor die.
17. The semiconductor package of claim 12 , further comprising a wirebond electrically connecting the package bump and the semiconductor die.
18. A semiconductor package,
comprising:
a first semiconductor die;
a bump layer disposed outside a footprint of the first semiconductor die and extending from a first level corresponding to a first surface of the first semiconductor die to a second level beyond a second surface of the first semiconductor die opposite the first surface of the first semiconductor die; and
an encapsulant deposited over the first semiconductor die and bump layer, wherein the encapsulant extends from the first level corresponding to the first surface of the first semiconductor die to a third level between the first level and the second level beyond the second surface of the first semiconductor die.
19. The semiconductor package of claim 18 , further including an underfill material disposed around the first semiconductor die.
20. The semiconductor package of claim 18 , further including an insulating layer disposed around the first semiconductor die.
21. The semiconductor package of claim 18 , further including a conductive layer formed between the bump layer and first semiconductor die.
22. The semiconductor package of claim 18 , further including a conductive layer formed over the encapsulant and electrically connected to the bump layer.
23. The semiconductor package of claim 18 , wherein the bump layer includes a plurality of layers of conductive material.
24. The semiconductor package of claim 18 , further including an insulating layer formed over the first semiconductor die.
25. The semiconductor package of claim 18 , further including a second semiconductor die disposed over the first semiconductor die.
26. The semiconductor package of claim 25 , further including a wirebond electrically connecting the first semiconductor die or the second semiconductor die and the bump layer.
27. The semiconductor package of claim 25 , further including a bump electrically connecting the second semiconductor die and the bump layer.
28. The semiconductor package of claim 18 , further including a conductive bump material formed over the bump layer.