Patent Assignment
Reel/Frame 038378/0352
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 8
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SIX, SLOVENIA
Covered Applications
(100)
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
App. No. 14/258,300
→
Semiconductor Device and Method of Making TSV Interconnect Structures Using Encapsulant for Structural Support
App. No. 14/143,891
→
SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
App. No. 14/063,274
→
SEMICONDUCTOR DEVICE HAVING BALANCED BAND-PASS FILTER IMPLEMENTED WITH LC RESONATORS
App. No. 14/018,282
→
Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation
App. No. 14/017,963
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR DIE DISPOSED IN A CAVITY OF AN INTERCONNECT STRUCTURE AND GROUNDED THROUGH THE DIE TSV
App. No. 13/935,312
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL DURING REFLOW WITH SOLDER MASK PATCH
App. No. 13/905,845
→
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
App. No. 13/845,329
→
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/727,116
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AIR GAP ADJACENT TO STRESS SENSITIVE REGION OF THE DIE
App. No. 13/706,818
→
Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die
App. No. 13/691,440
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP HAVING CONDUCTIVE LAYERS AND CONDUCTIVE VIAS SEPARATED BY POLYMER LAYERS
App. No. 13/679,792
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS
App. No. 13/606,451
→
Semicinductor Device with Cross-Talk Isolation Using M-CAP
App. No. 13/572,517
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP
App. No. 13/566,287
→
Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
App. No. 13/559,430
→
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die having Pre-Applied Protective Layer
App. No. 13/555,531
→
APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
App. No. 13/492,646
→
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING THERMALLY CONDUCTIVE LAYER IN INTERCONNECT STRUCTURE FOR HEAT DISSIPATION
App. No. 13/492,668
→
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
App. No. 13/476,899
→
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 13/446,741
→
METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/431,816
→
SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
App. No. 13/423,739
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
App. No. 13/423,263
→
Semiconductor Device and Method of Forming With Three-Dimensional Vertically Oriented Integrated Capacitors
App. No. 13/421,770
→
OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
App. No. 13/419,242
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE
App. No. 13/405,094
→
SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS IN PERIPHERAL REGION CONNECTING SHIELDING LAYER TO GROUND
App. No. 13/360,549
→
Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure
App. No. 13/356,485
→
SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
App. No. 13/339,185
→
SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR DIE WITH INTERNAL VERTICAL INTERCONNECT STRUCTURE AND METHOD THEREFOR
App. No. 13/335,631
→
Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor
App. No. 13/335,867
→
Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers
App. No. 13/312,852
→
Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
App. No. 13/273,537
→
Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
App. No. 13/248,312
→
SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
App. No. 13/245,099
→
SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
App. No. 13/241,153
→
SEMICONDUCTOR DEVICE WITH CONDUCTIVE VIAS BETWEEN SAW STREETS
App. No. 13/228,248
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFORMING CONDUCTIVE VIAS BETWEEN INSULATING LAYERS IN SAW STREETS
App. No. 13/228,226
→
SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING BALUN AND RF COUPLER ON A COMMON SUBSTRATE
App. No. 13/219,374
→
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
App. No. 13/218,653
→
APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
App. No. 13/212,986
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
App. No. 13/209,620
→
Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof
App. No. 13/181,838
→
Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
App. No. 13/174,033
→
Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street
App. No. 13/171,341
→
WAFER LEVEL DIE INTEGRATION AND METHOD THEREFOR
App. No. 13/170,116
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THREE-DIMENSIONAL VERTICALLY ORIENTED INTEGRATED CAPACITORS
App. No. 13/155,312
→
WIREBONDLESS WAFER LEVEL PACKAGE WITH PLATED BUMPS AND INTERCONNECTS
App. No. 13/101,657
→
SEMICONDUCTOR DEVICE HAVING IPD STRUCTURE WITH SMOOTH CONDUCTIVE LAYER AND BOTTOM-SIDE CONDUCTIVE LAYER
App. No. 13/090,590
→
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/019,562
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD
App. No. 13/019,541
→
WAFER INTEGRATED WITH PERMANENT CARRIER AND METHOD THEREFOR
App. No. 13/004,111
→
SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING THE SAME
App. No. 12/950,591
→
SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE
App. No. 12/941,683
→
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 12/912,467
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING A THERMAL DISSIPATION PATH THROUGH RDL AND CONDUCTIVE VIA
App. No. 12/911,042
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERPOSER PACKAGE WITH THROUGH SILICON VIAS
App. No. 12/905,825
→
ENCAPSULANT CAVITY INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF FABRICATION THEREOF
App. No. 12/892,907
→
INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG
App. No. 12/880,415
→
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-Up Interconnect Structure
App. No. 12/871,401
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
App. No. 12/832,821
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED PASSIVE DEVICES
App. No. 12/831,047
→
SEMICONDUCTOR DEVICE HAVING ELECTRICAL DEVICES MOUNTED TO IPD STRUCTURE AND METHOD OF SHIELDING ELECTROMAGNETIC INTERFERENCE
App. No. 12/830,390
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH-FREQUENCY CIRCUIT STRUCTURE AND METHOD THEREOF
App. No. 12/826,368
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE FOR ENCAPSULATED DIE HAVING PRE-APPLIED PROTECTIVE LAYER
App. No. 12/822,080
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR 3-D DEVICES USING ENCAPSULANT FOR STRUCTURAL SUPPORT
App. No. 12/775,188
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
App. No. 12/775,324
→
Semiconductor Device and Method of Forming an Interconnect Structure for 3-D Devices Using Encapsulant for Structural Support
App. No. 12/775,170
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
App. No. 12/775,338
→
GROOVING BUMPED WAFER PRE-UNDERFILL SYSTEM
App. No. 12/763,390
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE
App. No. 12/759,158
→
FUSIBLE I/O INTERCONNECTION SYSTEMS AND METHODS FOR FLIP-CHIP PACKAGING INVOLVING SUBSTRATE-MOUNTED STUD BUMPS
App. No. 12/731,330
→
FUSIBLE I/O INTERCONNECTION SYSTEMS AND METHODS FOR FLIP-CHIP PACKAGING INVOLVING SUBSTRATE-MOUNTED STUD BUMPS
App. No. 12/731,354
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECESSED CONDUCTIVE VIAS IN SAW STREETS
App. No. 12/719,398
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 12/716,455
→
SEMICONDUCTOR PACKAGE WITH PASSIVATION ISLAND FOR REDUCING STRESS ON SOLDER BUMPS
App. No. 12/651,758
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED-DOWN RDL AND RECESSED THV IN PERIPHERAL REGION OF THE DEVICE
App. No. 12/641,958
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED PASSIVE CIRCUIT ELEMENTS INTERCONNECTED TO THROUGH HOLE VIAS
App. No. 12/627,884
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPLIANT STRESS RELIEF BUFFER AROUND LARGE ARRAY WLCSP
App. No. 12/625,975
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE USING SACRIFICIAL CARRIER
App. No. 12/615,428
→
SEMICONDUCTOR PACKAGE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO OPPOSITE SIDES OF TSV SUBSTRATE
App. No. 12/612,365
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
App. No. 12/572,568
→
SEMICONDUCTOR DEVICE WITH A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
App. No. 12/572,590
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE
App. No. 12/565,698
→
SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS
App. No. 12/547,439
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO HEAT SPREADER ON TEMPORARY CARRIER AND FORMING POLYMER LAYER AND CONDUCTIVE LAYER OVER THE DIE
App. No. 12/541,334
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DAM MATERIAL AROUND PERIPHERY OF DIE TO REDUCE WARPAGE
App. No. 12/540,240
→
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
App. No. 12/533,270
→
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
App. No. 12/533,344
→
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
App. No. 12/533,160
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/486,568
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS WITH TRENCH IN SAW STREET
App. No. 12/484,143
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/483,087
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/474,757
→
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
App. No. 12/471,180
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SLOTTED DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/467,133
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
App. No. 12/434,367
→
SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/423,320
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH Z-INTERCONNECTS HAVING TRACES AND METHOD OF MANUFACTURE THEREOF
App. No. 12/412,312
→