Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.
1. A method of making a semiconductor device, comprising:
forming a plurality of first vertical conductive structures within the semiconductor device;
forming an insulating layer over the first vertical conductive structures;
forming a conductive layer over the insulating layer and first vertical conductive structures as a vertically oriented capacitor; and
depositing an encapsulant over the vertically oriented capacitor with the encapsulant extending down between the first vertical conductive structures.
2. The method of claim 1 , further including:
disposing a first semiconductor die within the semiconductor device; and
depositing the encapsulant over the first semiconductor die.
3. The method of claim 2 , further including:
forming a first interconnect structure over a first surface of the encapsulant;
forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant; and
forming a plurality of second vertical conductive structures between the first interconnect structure and second interconnect structure.
4. The method of claim 3 , wherein the first interconnect structure includes an integrated passive device.
5. The method of claim 3 , further including disposing a second semiconductor die over the first interconnect structure or second interconnect structure.
6. The method of claim 2 , wherein the vertically oriented capacitor extends along the semiconductor die.
7. The method of claim 1 , wherein the first vertical conductive structures include a plurality of conductive pillars.
8. A method of making a semiconductor device, comprising:
providing a substrate;
forming a seed layer over the substrate;
forming a conductive pillar over the seed layer;
conformally applying an insulating layer over the conductive pillar;
conformally applying a conductive layer over the insulating layer as a vertically oriented capacitor; and
removing the substrate to expose the seed layer.
9. The method of claim 8 , further including:
providing a first semiconductor die within the semiconductor device; and
depositing an encapsulant over the first semiconductor die and vertically oriented capacitor.
10. The method of claim 9 , wherein the vertically oriented capacitor extends along the first semiconductor die.
11. The method of claim 9 , further including:
forming a first interconnect structure over a first surface of the encapsulant;
forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant; and
forming a vertical conductive structure between the first interconnect structure and second interconnect structure.
12. The method of claim 11 , wherein the first interconnect structure includes an integrated passive device.
13. The method of claim 11 , further including disposing a second semiconductor die over the first interconnect structure or second interconnect structure.
14. The method of claim 9 , further including removing a portion of the seed layer to expose the first semiconductor die.
15. A method of making a semiconductor device, comprising:
forming a vertically oriented capacitor within the semiconductor device;
disposing a first semiconductor die or component within the semiconductor device;
forming a vertical conductive structure within the semiconductor device around the first semiconductor die or component, the vertical conductive structure including a height greater than a height of the vertically oriented capacitor; and
depositing an encapsulant over the vertically oriented capacitor, vertical conductive structure, and first semiconductor die or component.
16. The method of claim 15 , wherein forming the vertically oriented capacitor includes:
forming a conductive pillar within the semiconductor device;
forming an insulating layer over the conductive pillar; and
forming a conductive layer over the insulating layer.
17. The method of claim 15 , further including:
forming a first interconnect structure over a first surface of the encapsulant;
forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant; and
forming the vertical conductive structure between the first interconnect structure and second interconnect structure.
18. The method of claim 17 , wherein the first interconnect structure includes an integrated passive device.
19. The method of claim 17 , further including disposing a second semiconductor die or component over the first interconnect structure or second interconnect structure.
20. The method of claim 15 , wherein the vertically oriented capacitor extends along the first semiconductor die or component.
21. A method of making a semiconductor device, comprising:
forming a vertically oriented capacitor within the semiconductor device;
disposing a first semiconductor die or component within the semiconductor device;
depositing an encapsulant over the vertically oriented capacitor and first semiconductor die or component;
forming a first interconnect structure over a first surface of the encapsulant; and
forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant.
22. The method of claim 21 , wherein forming the vertically oriented capacitor includes:
forming a conductive pillar within the semiconductor device;
forming an insulating layer over the conductive pillar; and
forming a conductive layer over the insulating layer.
23. The method of claim 21 , further including forming a vertical conductive structure between the first interconnect structure and second interconnect structure.
24. The method of claim 21 , wherein the first interconnect structure includes an integrated passive device.
25. The method of claim 21 , further including disposing a second semiconductor die or component over the first interconnect structure or second interconnect structure.
26. The method of claim 21 , wherein the vertically oriented capacitor extends along the first semiconductor die or component.
27. A method of making a semiconductor device, comprising:
forming a conductive pillar within the semiconductor device;
conformally applying forming an insulating layer over the conductive pillar;
conformally applying forming a conductive layer over the insulating layer as a vertically oriented capacitor;
disposing a first semiconductor die over the substrate; and
depositing an encapsulant over the first semiconductor die and vertically oriented capacitor.
28. The method of claim 27 , further including:
forming a first interconnect structure over a first surface of the encapsulant; and
forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant.
29. The method of claim 28 , further including forming a vertical conductive structure between the first interconnect structure and second interconnect structure.
30. The method of claim 28 , wherein the first interconnect structure includes an integrated passive device.
31. The method of claim 28 , further including disposing a second semiconductor die over the first interconnect structure or second interconnect structure.
32. The method of claim 27 , wherein the vertically oriented capacitor extends along the first semiconductor die.
33. A semiconductor device, comprising:
a conductive pillar disposed within the semiconductor device;
an insulating layer conformally applied over the conductive pillar;
a conductive layer conformally applied over the insulating layer as a vertically oriented capacitor;
a semiconductor die disposed within the semiconductor device; and
an encapsulant deposited over the semiconductor die and vertically oriented capacitor.
34. The semiconductor device of claim 33 , further including:
a first interconnect structure formed over a first surface of the encapsulant;
a second interconnect structure formed over a second surface of the encapsulant opposite the first surface of the encapsulant and
a vertical conductive structure formed between the first interconnect structure and second interconnect structure.
35. The semiconductor device of claim 33 , wherein the vertically oriented capacitor extends along the semiconductor die.