IP Library Granted Patent US 8,159,047
Granted Patent B2
US 8,159,047 · App. 13/155,312 · Granted Apr 17, 2012

Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors

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Quick Facts
Patent No.
US 8,159,047
App. No.
13/155,312
Granted
Apr 17, 2012
Kind
B2
Abstract

A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.

Claims (58)

1. A semiconductor device comprising:

a seed layer;

a first conductive pillar disposed vertically over the seed layer;

a second conductive pillar disposed over the seed layer;

a conformal insulating layer formed over the first conductive pillar;

a conformal conductive layer formed over the conformal insulating layer, wherein the first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor;

a semiconductor die or component mounted over the seed layer; and

a first interconnect structure electrically connected to the second conductive pillar.

2. The semiconductor device of claim 1 , wherein the first interconnect structure comprises an integrated passive device.

3. The semiconductor device of claim 1 , further comprising an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, the first interconnect structure formed over a first side of the encapsulant.

4. The semiconductor device of claim 3 , wherein the first interconnect structure comprises:

a first conductive layer formed over the encapsulant, the first conductive layer electrically connected to the second conductive pillar;

a first insulating layer formed over the encapsulant and the first conductive layer;

a second conductive layer formed over the first insulating layer and the first conductive layer; and

a second insulating layer formed over the first insulating layer and the second conductive layer.

5. The semiconductor device of claim 3 , further comprising a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.

6. The semiconductor device of claim 1 , further comprising a second semiconductor die mounted to the first interconnect structure.

7. A semiconductor device, comprising:

conductive pillars including a first conductive pillar and a second conductive pillar;

a conformal insulating layer formed over the conductive pillars;

a conformal conductive layer formed over the conformal insulating layer, wherein the first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor;

a semiconductor die or component mounted over the conformal conductive layer and between the conductive pillars; and

a first interconnect structure electrically connected to the semiconductor die or component and vertically oriented integrated capacitor.

8. The semiconductor device of claim 7 , further comprising an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, the first interconnect structure formed over a first side of the encapsulant.

9. The semiconductor device of claim 8 , the first interconnect structure electrically connected to the second conductive pillar.

10. The semiconductor device of claim 9 , wherein the first interconnect structure comprises:

a first conductive layer formed over the encapsulant, the first conductive layer electrically connected to the second conductive pillar;

a first insulating layer formed over the encapsulant and first conductive layer;

a second conductive layer formed over the first insulating layer and first conductive layer; and

a second insulating layer formed over the first insulating layer and second conductive layer.

11. The semiconductor device of claim 8 , further comprising a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.

12. The semiconductor device of claim 7 , the first interconnect structure comprising an integrated passive device.

13. The semiconductor device of claim 7 , further comprising a second semiconductor die mounted to the first interconnect structure.

14. The semiconductor device of claim 13 , wherein the second semiconductor die is a flip chip type semiconductor die.

15. A semiconductor device, comprising:

a conductive pillar;

a conformal insulating layer formed over the conductive pillar;

a conformal conductive layer formed over the conformal insulating layer, wherein the conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor; and

a semiconductor die or component mounted over the conformal conductive layer.

16. The semiconductor device of claim 15 , further comprising an encapsulant deposited over the semiconductor die or component and around the vertically oriented integrated capacitor.

17. The semiconductor device of claim 16 , further comprising:

a first interconnect structure formed over a first side of the encapsulant, the first interconnect structure being electrically connected to the semiconductor die or component and vertically oriented integrated capacitor; and

a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.

18. The semiconductor device of claim 17 , wherein the first interconnect structure comprises an integrated passive device.

19. The semiconductor device of claim 17 , further comprising a second semiconductor die mounted to the first interconnect structure.

20. A semiconductor device, comprising:

a carrier;

a semiconductor die or component mounted over the carrier; and

a vertically oriented integrated metal-insulator-metal (MIM) capacitor disposed over the carrier, wherein an active surface of the semiconductor die or component is perpendicular to a first electrode and a second electrode of the vertically oriented integrated MIM capacitor, the first electrode comprising a conductive pillar having a cross-section in a plane that is perpendicular to the active surface of the semiconductor die or component with a height of the cross-section being greater than a width of the cross-section.

21. The semiconductor device of claim 20 , wherein the second electrode comprises a conformal conductive layer disposed over the conductive pillar.

22. The semiconductor device of claim 21 , wherein the vertically oriented integrated metal-insulator-metal (MIM) capacitor further comprises a conformal insulating layer disposed between the conductive pillar and the conformal conductive layer.

23. A semiconductor device, comprising:

a carrier;

a semiconductor die or component mounted over the carrier;

a vertically oriented integrated metal-insulator-metal (MIM) capacitor disposed over the carrier, wherein an active surface of the semiconductor die or component is perpendicular to a first electrode and a second electrode of the vertically oriented integrated MIM capacitor;

an encapsulant deposited over the semiconductor die or component and around the vertically oriented integrated MIM capacitor;

a first interconnect structure formed over a first side of the encapsulant, the first interconnect structure being electrically connected to the semiconductor die or component and the vertically oriented integrated MIM capacitor; and

a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
RELEASE OF SECURITY INTEREST Recorded Jun 8, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052864/0057 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0352 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →