Patent Assignment
Reel/Frame 064789/0474
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280)
Recorded: 2023-08-31
Received: 2023-08-31
Pages: 11
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(74)
METHOD FOR MANUFACTURING BALL GRID ARRAY PACKAGE STACKING SYSTEM
App. No. 13/269,258
→
METHOD FOR MANUFACTURING INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDER PADDLE LEADFINGERS
App. No. 13/172,560
→
INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM
App. No. 13/166,417
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THREE-DIMENSIONAL VERTICALLY ORIENTED INTEGRATED CAPACITORS
App. No. 13/155,312
→
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/019,562
→
PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/017,388
→
WAFER INTEGRATED WITH PERMANENT CARRIER AND METHOD THEREFOR
App. No. 13/004,111
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THROUGH SEMICONDUCTOR VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/974,866
→
SEMICONDUCTOR DEVICE AND METHOD OF DISSIPATING HEAT FROM THIN PACKAGE-ON-PACKAGE MOUNTED TO SUBSTRATE
App. No. 12/965,584
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/892,941
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
App. No. 12/832,821
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING AND ANTI-FLASH STRUCTURE
App. No. 12/831,822
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH-FREQUENCY CIRCUIT STRUCTURE AND METHOD THEREOF
App. No. 12/826,368
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADED PACKAGE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/822,954
→
METHOD OF FORMING TOP ELECTRODE FOR CAPACITOR AND INTERCONNECTION IN INTEGRATED PASSIVE DEVICE (IPD)
App. No. 12/763,386
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERMEDIATE PAD AND METHOD OF MANUFACTURE THEREOF
App. No. 12/732,423
→
INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES AND METHOD OF MANUFACTURE THEREOF
App. No. 12/715,910
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THIN FILM CAPACITOR
App. No. 12/705,810
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPACT COILS FOR HIGH PERFORMANCE FILTER
App. No. 12/705,790
→
METHOD OF FORMING THIN PROFILE WLCSP WITH VERTICAL INTERCONNECT OVER PACKAGE FOOTPRINT
App. No. 12/696,923
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL ROW LEAD-FRAME HAVING TOP AND BOTTOM TERMINALS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/635,699
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/633,789
→
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 12/624,482
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING IPD ON MOLDED SUBSTRATE
App. No. 12/621,738
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPEN CAVITY IN TSV INTERPOSER TO CONTAIN SEMICONDUCTOR DIE IN WLCSMP
App. No. 12/565,380
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE
App. No. 12/557,811
→
SEMICONDUCTOR DEVICE AND METHOD OF STACKING DIE ON LEADFRAME ELECTRICALLY CONNECTED BY CONDUCTIVE PILLARS
App. No. 12/545,357
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH VIA DIE HAVING PEDESTAL AND RECESS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/486,271
→
INTERCONNECTING A CHIP AND A SUBSTRATE BY BONDING PURE METAL BUMPS AND PURE METAL SPOTS
App. No. 12/472,083
→
A METHOD OF A PACKAGE ON PACKAGE PACKAGING
App. No. 12/468,810
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OVERLAPPING SEMICONDUCTOR DIE WITH COPLANAR VERTICAL INTERCONNECT STRUCTURE
App. No. 12/467,865
→
FLIP CHIP INTERCONNECTION PAD LAYOUT
App. No. 12/432,137
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/411,040
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NO-FLOW UNDERFILL MATERIAL AROUND VERTICAL INTERCONNECT STRUCTURE
App. No. 12/410,312
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE
App. No. 12/406,049
→
DOUBLE-SIDED SEMICONDUCTOR DEVICE AND METHOD OF FORMING TOP-SIDE AND BOTTOM-SIDE INTERCONNECT STRUCTURES
App. No. 12/332,799
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE IN SUBSTRATE FOR IPD AND BASEBAND CIRCUIT SEPARATED BY HIGH-RESISTIVITY MOLDING COMPOUND
App. No. 12/329,789
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BOND WIRES AND STUD BUMPS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
App. No. 12/329,800
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/328,717
→
INTEGRATED CIRCUIT PACKAGING SYSTEM USING BOTTOM FLIP CHIP DIE BONDING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/328,722
→
INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF PACKAGE STACKING
App. No. 12/273,541
→
METHOD OF ELECTRICALLY CONNECTING A SHIELDING LAYER TO GROUND THROUGH A CONDUCTIVE VIA DISPOSED IN PERIPHERAL REGION AROUND SEMICONDUCTOR DIE
App. No. 12/238,007
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE HAVING RELIEVED ACTIVE REGION
App. No. 12/235,111
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE IN NON-ACTIVE AREA OF WAFER
App. No. 12/207,324
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FLIP CHIP
App. No. 12/194,507
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONCAVE TERMINAL
App. No. 12/185,616
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE
App. No. 12/144,931
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULATION
App. No. 12/143,047
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFINGER
App. No. 12/134,179
→
OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
App. No. 12/044,688
→
PACKAGE SYSTEM FOR SHIELDING SEMICONDUCTOR DIES FROM ELECTROMAGNETIC INTERFERENCE
App. No. 12/037,774
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PASSIVE DEVICES
App. No. 11/958,546
→
MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE HAVING A CONDUCTOR-FREE RECESS
App. No. 11/927,646
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE
App. No. 11/860,460
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
App. No. 11/859,359
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY
App. No. 11/857,402
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE ENCAPSULATION HAVING RECESS
App. No. 11/855,114
→
NESTED INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
App. No. 11/849,263
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THIN PROFILE
App. No. 11/750,218
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONDUCTIVE SPACER
App. No. 11/694,927
→
BRIDGE STACK INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM
App. No. 11/616,878
→
SEMICONDUCTOR WAFER SCALE PACKAGE SYSTEM
App. No. 11/615,923
→
INTEGRATED CIRCUIT SYSTEM WITH METAL-INSULATOR-METAL CIRCUIT ELEMENT
App. No. 11/469,576
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN EXPOSED THERMALLY CONDUCTIVE COATING
App. No. 11/458,078
→
INTEGRATED CIRCUIT MOUNT SYSTEM WITH SOLDER MASK PAD
App. No. 11/456,551
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-PLANAR PADDLE
App. No. 11/381,684
→
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING INTERCONNECT STACK AND EXTERNAL INTERCONNECT
App. No. 11/276,716
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE ON BASE PACKAGE
App. No. 11/307,723
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/307,128
→
BUMP CHIP CARRIER SEMICONDUCTOR PACKAGE SYSTEM
App. No. 11/306,806
→
WAFER STRENGTH REINFORCEMENT SYSTEM FOR ULTRA THIN WAFER THINNING
App. No. 11/306,098
→
HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM COMPRISING HEAT SLUGS ON OPPOSITE SURFACES OF A SEMICONDUCTOR CHIP
App. No. 11/164,209
→
SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HEAT SINK
App. No. 11/164,132
→
INTEGRATED CIRCUIT PACKAGE SYSTEM USING ETCHED LEADFRAME
App. No. 11/163,305
→