Method of forming thin profile WLCSP with vertical interconnect over package footprint

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die each with an active surface;

mounting a second semiconductor die to the first semiconductor die, the active surface of the first semiconductor die being oriented toward an active surface of the second semiconductor die;

depositing an encapsulant over the first and second semiconductor die;

removing a portion of a back surface of the second semiconductor die opposite the active surface;

forming conductive pillars around the second semiconductor die;

forming an interconnect structure over the back surface of the second semiconductor die, encapsulant, and conductive pillars, the interconnect structure being electrically connected to the conductive pillars;

removing a portion of a back surface of the first semiconductor die opposite the active surface; and

singulating the semiconductor wafer into individual semiconductor devices.

2. The method of claim 1 , further including mounting a discrete semiconductor component to the first semiconductor die.

3. The method of claim 1 , further including forming a conductive via through the first semiconductor die.

4. The method of claim 1 , further including forming a heat sink over the back surface of the first semiconductor die.

5. The method of claim 1 , further including forming a shielding layer over the back surface of the first semiconductor die.

6. The method of claim 1 , further including mounting side-by-side semiconductor die over the first semiconductor die.

7. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die each with an active surface;

mounting a second semiconductor die to the first semiconductor die, the active surface of the first semiconductor die being oriented toward an active surface of the second semiconductor die;

forming a vertical interconnect structure around the second semiconductor die;

depositing an encapsulant over the first and second semiconductor die;

removing a portion of a back surface of the second semiconductor die opposite the active surface;

forming a build-up interconnect structure over the back surface of the second semiconductor die, encapsulant, and vertical interconnect structure, the build-up interconnect structure being electrically connected to the vertical interconnect structure;

removing a portion of a back surface of the first semiconductor die opposite the active surface; and

singulating the semiconductor wafer into individual semiconductor devices.

8. The method of claim 7 , further including mounting a discrete semiconductor component to the first semiconductor die.

9. The method of claim 7 , further including forming a conductive via through the first semiconductor die.

10. The method of claim 7 , further including forming a heat sink over the back surface of the first semiconductor die.

11. The method of claim 7 , further including forming a shielding layer over the back surface of the first semiconductor die.

12. The method of claim 7 , wherein the vertical interconnect structure includes a conductive pillar, stacked bumps, post and pillar, or bump and pillar.

13. The method of claim 7 , wherein forming the vertical interconnect structure includes:

mounting a leadframe interposer over the first and second semiconductor die prior to depositing the encapsulant, the leadframe interposer including plate and bodies extending from the plate to the first semiconductor die;

depositing the encapsulant over the first and second semiconductor die and around the bodies of the leadframe interposer; and

removing the plate to leave the bodies in the encapsulant as conductive pillars around the second semiconductor die.

14. A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor die having an active surface;

mounting a second semiconductor die to the first semiconductor die, the active surface of the first semiconductor die being oriented toward an active surface of the second semiconductor die;

forming a vertical interconnect structure around the second semiconductor die;

depositing an encapsulant over the first and second semiconductor die;

removing a portion of a back surface of the second semiconductor die opposite the active surface;

forming a build-up interconnect structure over the back surface of the second semiconductor die, encapsulant, and vertical interconnect structure, the build-up interconnect structure being electrically connected to the vertical interconnect structure; and

removing a portion of a back surface of the first semiconductor die opposite the active surface.

15. The method of claim 14 , further including mounting a discrete semiconductor component to the first semiconductor die.

16. The method of claim 14 , further including forming a conductive via through the first semiconductor die.

17. The method of claim 14 , further including forming a heat sink over the back surface of the first semiconductor die.

18. The method of claim 14 , further including forming a shielding layer over the back surface of the first semiconductor die.

19. The method of claim 14 , wherein the vertical interconnect structure includes a conductive pillar, stacked bumps, post and pillar, or bump and pillar.

20. The method of claim 14 , wherein forming the vertical interconnect structure includes:

mounting a leadframe interposer over the first and second semiconductor die prior to depositing the encapsulant, the leadframe interposer including plate and bodies extending from the plate to the first semiconductor die;

depositing the encapsulant over the first and second semiconductor die; and

removing the plate to leave the bodies in the encapsulant as conductive pillars around the second semiconductor die.