IP Library Granted Patent US 8,138,080
Granted Patent B2
US 8,138,080 · App. 11/276,716 · Granted Mar 20, 2012

Integrated circuit package system having interconnect stack and external interconnect

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,138,080
App. No.
11/276,716
Granted
Mar 20, 2012
Kind
B2
Abstract

An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.

Claims (50)

1. A method of manufacturing an integrated circuit package system comprising:

forming an integrated circuit die having a first bond pad provided thereon;

forming an interconnect stack having a wire stitch directly on a first external interconnect and a ball bond directly on the wire stitch, the interconnect stack having an equal number of wire stitches and ball bonds with one of the ball bonds as a topmost part of the interconnect stack;

connecting the interconnect stack to the first bond pad; and

forming an encapsulation covering the integrated circuit die, the interconnect stack, and the first external interconnect with the first external interconnect exposed from the encapsulation.

2. The method as claimed in claim 1 wherein forming the interconnect stack comprises:

attaching a first interconnect on the first external interconnect;

forming a first ball bond on the first interconnect;

attaching a second interconnect on the first ball bond; and

forming a second ball bond on the second interconnect.

3. The method as claimed in claim 1 further comprising connecting the interconnect stack to a group of first bond pads of the integrated circuit die.

4. The method as claimed in claim 1 further comprising connecting an interconnect between a second external interconnect and a second bond pad of the integrated circuit die.

5. The method as claimed in claim 1 further comprising attaching the integrated circuit die on a die paddle adjacent to the first external interconnect.

6. A method of manufacturing an integrated circuit package system comprising:

forming an integrated circuit die having a first bond pad provided thereon;

forming a interconnect stack having a wire stitch directly on a first lead and a ball bond directly on the wire stitch, the interconnect stack having an equal number of wire stitches and ball bonds with one of the ball bonds as a topmost part of the interconnect stack;

connecting the interconnect stack on a first bond pad; and

forming an encapsulation covering the integrated circuit die, the interconnect stack, and the first lead with the first lead exposed from the encapsulation.

7. The method as claimed in claim 6 wherein forming the interconnect stack comprises:

attaching a first wire stitch on the first lead;

forming a first ball bond on the first wire stitch;

attaching a second wire stitch on the first ball bond; and

forming a second ball bond on the second wire stitch.

8. The method as claimed in claim 6 further comprising connecting an interconnect between a second lead and a second bond pad of the integrated circuit die.

9. The method as claimed in claim 6 further comprising forming first bond pads of the integrated circuit die is in a configuration of an array.

10. The method as claimed in claim 6 further comprising forming first bond pads of the integrated circuit die is at a boundary of the integrated circuit die.

11. An integrated circuit package system comprising:

an integrated circuit die having a first bond pad provided thereon;

an interconnect stack having a wire stitch directly on a first external interconnect and a ball bond directly on the wire stitch, the interconnect stack connected to the first bond pad, the interconnect stack having an equal number of wire stitches and ball bonds with one of the ball bonds as a topmost part of the interconnect stack; and

an encapsulation covering the integrated circuit die, the interconnect stack, and the first external interconnect with the first external interconnect exposed from the encapsulation.

12. The system as claimed in claim 11 wherein the interconnect stack comprises:

a first interconnect on the first external interconnect;

a first ball bond on the first interconnect;

a second interconnect on the first ball bond; and

a second ball bond on the second interconnect.

13. The system as claimed in claim 11 further comprising the interconnect stack connected to a group of first bond pads of the integrated circuit die.

14. The system as claimed in claim 11 further comprising an interconnect between a second external interconnect and a second bond pad of the integrated circuit die.

15. The system as claimed in claim 11 further comprising the integrated circuit die on a die paddle adjacent to the first external interconnect.

16. The system as claimed in claim 11 wherein:

the integrated circuit die having the first bond pad provided thereon has an active side;

the interconnect stack on the first external interconnect, the interconnect stack connected to the first bond pad has a wire; and

the first external interconnect is a first lead.

17. The system as claimed in claim 16 wherein the interconnect stack comprises:

a first wire stitch on the first lead;

a first ball bond on the first wire stitch;

a second wire stitch on the first ball bond; and

a second ball bond on the second wire stitch.

18. The system as claimed in claim 16 further comprising an interconnect between a second lead and a second bond pad of the integrated circuit die.

19. The system as claimed in claim 16 further comprising first bond pads of the integrated circuit die is in a configuration of an array.

20. The system as claimed in claim 16 further comprising first bond pads of the integrated circuit die is at a boundary of the integrated circuit die.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF EXECUTION OF 2/3/2006 FOR THE SIXTH ASSIGNOR, LIAGAN, ALLAN SHOULD BE 3/2/2006 PREVIOUSLY RECORDED ON REEL 017308 FRAME 0774. ASSIGNOR(S) HEREBY CONFIRMS THE 2/3/2006 DATE OF EXECUTION IS INCORRECT AND SHOULD BE 3/2/2006. Recorded Feb 16, 2012
From: ILAGAN, ALLAN
To: STATS CHIPPAC LTD.
Reel/Frame 027729/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2006
From: FILOTEO, JR., DARIO S.; MERILO, LEO A.; CABLAO, PHILIP LYNDON; ESPIRITU, EMMANUEL; ABINAN, RACHEL LAYDA; ILAGAN, ALLAN
To: STATS CHIPPAC LTD.
Reel/Frame 017308/0774 →