IP Library › Assignment 052879/0852
Patent Assignment
Reel/Frame 052879/0852

RELEASE OF SECURITY INTEREST

Recorded: 2020-06-09 Received: 2020-06-09 Pages: 27
Assignor
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications (100)
METHOD FOR MANUFACTURING BALL GRID ARRAY PACKAGE STACKING SYSTEM
App. No. 13/269,258
→
PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/017,388
→
STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/006,278
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THROUGH SEMICONDUCTOR VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/974,866
→
SEMICONDUCTOR DEVICE AND METHOD OF DISSIPATING HEAT FROM THIN PACKAGE-ON-PACKAGE MOUNTED TO SUBSTRATE
App. No. 12/965,584
→
EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/964,638
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIA WITH DIRECT INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/949,835
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/892,941
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH SIDE-BY-SIDE AND OFFSET STACKING AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/871,031
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER-LEVEL MULTI-ROW ETCHED LEADFRAME WITH BASE LEADS AND EMBEDDED SEMICONDUCTOR DIE
App. No. 12/857,395
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING AND ANTI-FLASH STRUCTURE
App. No. 12/831,822
→
SEMICONDUCTOR DEVICE HAVING ELECTRICAL DEVICES MOUNTED TO IPD STRUCTURE AND METHOD OF SHIELDING ELECTROMAGNETIC INTERFERENCE
App. No. 12/830,390
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH-FREQUENCY CIRCUIT STRUCTURE AND METHOD THEREOF
App. No. 12/826,368
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/782,992
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/777,023
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR 3-D DEVICES USING ENCAPSULANT FOR STRUCTURAL SUPPORT
App. No. 12/775,188
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD FOR MAKING THEREOF
App. No. 12/772,128
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERMEDIATE PAD AND METHOD OF MANUFACTURE THEREOF
App. No. 12/732,423
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON DIFFERENT HEIGHT TRACES
App. No. 12/720,029
→
INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES AND METHOD OF MANUFACTURE THEREOF
App. No. 12/715,910
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED CONDUCTOR AND METHOD OF MANUFACTURE THEREOF
App. No. 12/714,320
→
METHOD OF FORMING QUAD FLAT PACKAGE
App. No. 12/703,450
→
QUAD FLAT PACKAGE
App. No. 12/703,461
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL ROW LEAD-FRAME HAVING TOP AND BOTTOM TERMINALS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/635,699
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/633,789
→
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 12/624,482
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/608,587
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND MANUFACTURING METHOD THEREOF
App. No. 12/578,797
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
App. No. 12/562,414
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION
App. No. 12/544,555
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/488,555
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH VIA DIE HAVING PEDESTAL AND RECESS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/486,271
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE BETWEEN NON-LINEAR PORTIONS OF CONDUCTIVE LAYERS
App. No. 12/484,146
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
App. No. 12/480,317
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM FIXED RELATIVE TO INTERCONNECT STRUCTURE FOR ALIGNMENT OF SEMICONDUCTOR DIE
App. No. 12/476,447
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER INTERCONNECTIONS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/473,253
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INTERCONNECTING A CHIP AND A SUBSTRATE BY BONDING PURE METAL BUMPS AND PURE METAL SPOTS
App. No. 12/472,083
→
A METHOD OF A PACKAGE ON PACKAGE PACKAGING
App. No. 12/468,810
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OVERLAPPING SEMICONDUCTOR DIE WITH COPLANAR VERTICAL INTERCONNECT STRUCTURE
App. No. 12/467,865
→
FLIP CHIP INTERCONNECTION PAD LAYOUT
App. No. 12/432,137
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/411,040
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING PRE-FABRICATED SHIELDING FRAME OVER SEMICONDUCTOR DIE
App. No. 12/409,142
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE
App. No. 12/406,049
→
SEMICONDUCTOR DIE AND METHOD OF FORMING NOISE ABSORBING REGIONS BETWEEN THVS IN PERIPHERAL REGION OF THE DIE
App. No. 12/404,069
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL BOARD-ON-CHIP STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/398,466
→
DOUBLE-SIDED SEMICONDUCTOR DEVICE AND METHOD OF FORMING TOP-SIDE AND BOTTOM-SIDE INTERCONNECT STRUCTURES
App. No. 12/332,799
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INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING ASYMMETRIC ENCAPSULATION STRUCTURES AND METHOD OF MANUFACTURE THEREOF
App. No. 12/328,762
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/328,717
→
INTEGRATED CIRCUIT PACKAGING SYSTEM USING BOTTOM FLIP CHIP DIE BONDING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/328,722
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI LEVEL CONTACT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/273,547
→
INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF PACKAGE STACKING
App. No. 12/273,541
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED PAD AND METHOD OF MANUFACTURE THEREOF
App. No. 12/272,751
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SEMICONDUCTOR PACKAGE SYSTEM WITH THROUGH SILICON VIA INTERPOSER
App. No. 12/239,715
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METHOD OF ELECTRICALLY CONNECTING A SHIELDING LAYER TO GROUND THROUGH A CONDUCTIVE VIA DISPOSED IN PERIPHERAL REGION AROUND SEMICONDUCTOR DIE
App. No. 12/238,007
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE HAVING RELIEVED ACTIVE REGION
App. No. 12/235,111
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/194,506
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FLIP CHIP
App. No. 12/194,507
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONCAVE TERMINAL
App. No. 12/185,616
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE
App. No. 12/144,931
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULATION
App. No. 12/143,047
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BALL GRID ARRAY PACKAGE STACKING SYSTEM
App. No. 12/141,059
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEXIBLE SUBSTRATE AND RECESSED PACKAGE
App. No. 12/136,002
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SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
App. No. 12/133,216
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INSULATOR OVER CIRCUITRY
App. No. 12/126,684
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD AND TIE BAR
App. No. 12/124,793
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SYSTEM FOR SOLDER BALL INNER STACKING MODULE CONNECTION
App. No. 12/046,369
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OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
App. No. 12/044,688
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PACKAGE SYSTEM FOR SHIELDING SEMICONDUCTOR DIES FROM ELECTROMAGNETIC INTERFERENCE
App. No. 12/037,774
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
App. No. 12/037,291
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PASSIVE DEVICES
App. No. 11/958,546
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION
App. No. 11/957,845
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING
App. No. 11/954,603
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MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE HAVING A CONDUCTOR-FREE RECESS
App. No. 11/927,646
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DIE
App. No. 11/863,700
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE
App. No. 11/860,460
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
App. No. 11/859,359
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY
App. No. 11/857,402
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE ENCAPSULATION HAVING RECESS
App. No. 11/855,114
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH GROUND BONDS
App. No. 11/766,785
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THIN PROFILE
App. No. 11/750,218
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT MOLD LOCKING FEATURES
App. No. 11/749,693
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STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONDUCTIVE SPACER
App. No. 11/694,927
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INTEGRATED CIRCUIT PACKAGE WITH TOP PAD
App. No. 11/618,805
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SEMICONDUCTOR WAFER SCALE PACKAGE SYSTEM
App. No. 11/615,923
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/532,510
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/532,509
→
INTEGRATED CIRCUIT SYSTEM WITH METAL-INSULATOR-METAL CIRCUIT ELEMENT
App. No. 11/469,576
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN EXPOSED THERMALLY CONDUCTIVE COATING
App. No. 11/458,078
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INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING WAFER LEVEL SPACER
App. No. 11/456,845
→
INTEGRATED CIRCUIT MOUNT SYSTEM WITH SOLDER MASK PAD
App. No. 11/456,551
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-PLANAR PADDLE
App. No. 11/381,684
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INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING INTERCONNECT STACK AND EXTERNAL INTERCONNECT
App. No. 11/276,716
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE ON BASE PACKAGE
App. No. 11/307,723
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/307,128
→
BUMP CHIP CARRIER SEMICONDUCTOR PACKAGE SYSTEM
App. No. 11/306,806
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WAFER STRENGTH REINFORCEMENT SYSTEM FOR ULTRA THIN WAFER THINNING
App. No. 11/306,098
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SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HEAT SINK
App. No. 11/164,132
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METHOD OF MANUFACTURING NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING ETCHED DIFFERENTIAL HEIGHT LEAD STRUCTURES
App. No. 11/164,088
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PLANAR INTERCONNECTS
App. No. 11/162,629
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INTEGRATED CIRCUIT PACKAGE SYSTEM USING INTERPOSER
App. No. 11/162,635
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